Lecture 7 and 8

1
Lecture 7 and 8
2
Extended FSM models (RT-level)

• FSMs have normally only Boolean inputs as
  conditions and Boolean outputs
• Sequential logic has both control path and data
  path. How to describe?
• How can we include arithmetic in a FSM?
• One answer is to use a FSMD (FSM with Data path)

3
Extended FSM Models
Control path(FSM)
FSMD
Control signals
Status signals
Data path(ALU etc)
4
Extended FSM Models
Control signals
Condition signals
Data Path
5
Extended FSM Models (FSMD)
State name
Unconditional variable and output assignments
State box
Condition
0
1
Decision box
Conditional variable assignment
Condition box
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Extended FSM Models (FSMD)
s0
s0
Block
Block
s1
s1
s2
Cond assign
Moore type
Mealy type
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Extended FSM, UART Project

• We want to model the UART. Alternatives
• Sequential language model (just VHDL)
• State machine model (FSM) for control and data
  path. Control and condition signals between
  control path and data path.
• Extended FSM (FSMD with data path)
• Model can be manually synthesized to VHDL code
  which is automatically synthesized to logic

8
Extended FSM, UART Project
Buss interface
Bit rate generator
Bit rate 16
Receiver
Transmitter
FSM
FSM
RX Reg
TX Reg
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Extended FSM, UART Project
Synchronous clock and bit clock Do not gate the
clock but use a condition!
process begin if reset1 then
......... elsif clkevent and clk1 then
if bit_clk1 then -- bit clock one clk
period ......... end if
end if end process
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FSMD for UART Receiver
s2
s0
RXRDY1
Cnt160BitCnt0
RXRDY-set Strobe one system clock!
0
RX0
s1
BitCnt9
Cnt16Cnt161
0
Cnt167
0
RPar R(91)
RRX R(91)
BitCntBitCnt1
11
Design Productivity Gap
Moores Law The capacity of integrated chips
doubles every 18-20 months.
108
106
1
Time
65 75 80 85
90 95 2000
12
History of Automation in System Design

• Levels of Design Representation

System Functional Specification
? Behavioral Specification (VHDL)
? RTL Design, C-Code
? Logic Level Design, Machine Code
? Physical Design
? Implementation
2000 Partially
90s
85
80s
70s
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Y-Chart
Behavioral Domain
Structural Domain
Flowcharts, Algorithms Register Transfers
Processors, Mem, Buses Registers, ALUs, MuXs,
. Gates, Flip-Flops
- Transistors
Boolean Expressions Transistor Functions
Transistor Layout Cells, Modules Chips, ASICs
Boards, MCM
Physical Domain
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Y-Chart-AXES

• Behavioral Axis
• Represents functionality what the system is
  supposed to do.
• Structural Axis
• Represents the logical interconnections of
  components to build the system how the system is
  built by interconnecting sub-systems(components).
• Physical Axis
• Represents the physical implementation of the
  system.

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Design Representation in Y-Chart
Behavioral Domain
Structural Domain
Functional Design
Flowcharts, Algorithms Register Transfers
Processors, Mem, Buses Registers, ALUs, MuXs,
. Gates, Flip-Flops
- Transistors
Boolean Expressions Transistor Functions
Transistor Layout Cells, Modules Chip, ASIC
Physical Design of a chip

• As we move towards the center, we add more
  details

Boards, MCM
Physical Domain
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Representation of Design Processes
Behavioral Domain
Synthesis
Structural Domain
Flowcharts, Algorithms Register Transfers
Processors, Mem, Buses Registers, ALUs, MuXs,
. Gates, Flip-Flops
- Transistors
Boolean Expressions Transistor Functions
Transistor Layout Cells, Modules Chips, ASICs
Implementation
Boards, MCM
Physical Domain
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High level design / Simulation
The efficiency of the designer will increase if
she/he designs at a higher abstraction
level. Its possible to design and simulate VHDL
on a Behavioural level. The data types etc can be
more freely chosen. Special synthesis tools are
required to synthesize on behavioural level!
Note the difference between behavioural level and
behavioural synthesis! We will come to
Behavioural synthesis later in this lecture
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Synthesis
Synthesis involves the transformation of system
description from behavioral domain to structural
domain.

• Behavioral Synthesis
• Algorithmic description gt RTL-design
• RTL-design Design using Registers, adders, muxes
  etc.
• Logic Synthesis
• Boolean functions, Finite State Machines gt Logic
  Design
• Logic design Design using gates and flip-flops.

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Synthesizable/Executable Spec.

• Executable Specification
• It is possible to simulate the specification to
  determine system behaviour. Some languages give
  clock accurate simulation (e.g. SystemC).
• Synthesizable Specification
• It is possible to build hardware with equivalent
  timing and functional behaviour to the
  specification.
• (A subset of VHDL is synthesizable)

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Synthesizable VHDL Examples
Simulation
Architecture XYZ of PQR is Signal S1, S2,
S3 Begin S2 lt X and Y S3 lt
S2 or Y after 3 ns End
Y S2 S3
X Y
S2 S3

?1
It is not possible to ensure the delay to be
exact 3 ns.
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Behavioral and RTL Synthesis
x
x
-

4 cycles15 ns
Behavioral Synthesis
x
-

3 cycles15 ns
x
Vary clock period Vary of clock periods
x
-

2 cycles20 ns
x
HDL Description Za(i)b(i)-cd(k)f
Multiple Architectures
RTL Synthesis
x
-

1 cycle55 ns
x
Vary clock period 1 clock cycle
Single Architectures
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Behavioral Synthesis Illustration
ENTITY gcd IS PORT (x_in,y_in IN bit8 z_out
OUT bit8 clock, start IN BIT ready OUT
BIT) END gcd ARCHITECTURE beh_gcd IS BEGIN
PROCESS Variable x,y,z bit8 BEGIN
WAIT UNTIL start 1 X x_in Y y_in
WHILE NOT( XY) LOOP IF X gt Y THEN X
X- Y ELSE Y Y-X WAIT UNTIL
clockevent END LOOP Z_out X ready
1 END Process
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Behavioral Synthesis/High Level Synthesis
Behavioral synthesis translates the behavioral
HDL (VHDL) description to RTL-design (Register
Transfer Level). Reuse of resources! Control of
resource usage done by Control Unit ( comapare to
RTL-level) Behavioral Synthesis Steps

• Scheduling
• To decide time for each operation
• Constrains on resources or time
• Allocation
• Resources Registers, Memories, ALUs, buses etc.
• To decide the type and number of resources
  required.
• Binding
• Deciding a specific ALU for each operation
• Deciding a specific register for each varible.

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Behavioral Synthesis/High Level Synthesis

• Data path A number of interconnected components
  on RTL-level
• Control Unit FSM that generates control signals
  for Data path
• Scheduling
• To decide time for each operation. Determine in
  which clock cycle a resource shall be executed.
  Different function can use the same resource but
  not at the same time. The scheduler is
  implemented as a State machine (control unit).
• Allocation
• Allocate resources to operators. Decide the type
  and number of resources required.
• Binding
• Bind a special resource to a special operation
• Latency Number of clock cycles required to
  execute a function.
• Throughput How often new data can be clocked
  into the system.

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Behavioral Synthesis/High Level Synthesis
1



2
2
The resources shall be scheduled so the resource
with the longest path to end shall be scheduled
first. (one method)

3

3

4
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Behavioral Synthesis/High Level Synthesis

• Handshaking / Process synchronization
• VHDL code can be correctly simulated on
  behavioural level. Its clock accurate.
• After Behavioural synthesis the cycle-to-cycle
  behaviour is changed (due to scheduling and
  resource allocation).
• The processes must be synchronized by handshake
  signals

data
ready
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Behavioural synthesis
For special purposes a HW, designed by
Behavioural Synthesis, can replace a micro
controller and SW (SPPSingle Purpose
Processor). Less over headFaster
Example Scheduler in a Real time kernel in HW.
RealFast in Västerås
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Technology Mapping
Technology mapping process converts a technology
independent design into a netlist of components
from a particular technology

• Technology independent design (generic)
• Gates with any number of inputs or outputs.
• Register of any size and with any number of
  control signals.
• Technology dependent components
• A gate with 2 inputs and a specified fan-out.
• A gate optimized for speed.
• A gate optimized for area.
• Etc.

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System Modelling
C has been used for system modelling and then
refined with VHDL. Newer methods SDL,
Specification and Description Language
(graphical)SystemC (Class library to C for HW
modelling) EFSM Extended Finite State Machine
(data path and control path). Control path
generated by tool.
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System Modelling
HW and SW co-design and co-simulation. Tools to
partion HW and SW New tools or extended old
tools Examples
C / VHDL
1)
SystemC (C with class libraries for hardware
and communication modelling)
2)
Superlog (extended Verilog)
3)
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IP, Intellectual Property
Virtual components / Cores The design efficiency
can be increased if tested components are reused.
Such virtual components are called IP
(Intellectual Property). Hard IP Technology
mapped for a special process or FPGA.Soft IP
Synthesible HDL description (VHDL, Verilog,
SystemC etc).
Examples of IP blocks Cores Micro
controllers, DSP, DES encryption modules
etc. IO-block DRAM-controller, UART, USB,
Firewire etc
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SoC System On Chip
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SoC / SOPC System On Programmable Chip
New technology (small scale) has high NRE
(Nonrecurring Engineering Cost). (1.2 gt 0.6 gt
0.35 gt 0.25 gt 0.15 gt 0.13 gt0,09 ( ??
?m) Today (2003) NRE (0.13 ?m)
500k-1000k(Write off for a fab is 2Bn over 3
years)
Q Who can afford this?A Big companies with
very high volumes.Q Why do we then study System
Level Design? In Sweden only Ericsson designs
such circuits.A FPGAs with built in, hard or
soft cores, also require system level design
methods.
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NOC Network on Chip (ING Research)
network (packet swiched)
switch
resourcee.g. CPU
0110
0110
35
Seems interesting?
If System level design seems interesting If Logic
synthesis seems interesting If Advanced HW design
seems interesting Apply for the Master
program in Embedded Systems!
36
ASIC
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ASIC Application Specific Integrated
Circuit Gate Array Prefabricated wafer with
logicadded interconnections (metal layers). Vol
gt 10k Standard Cell Library with components
(e.g. gates, multiplexors, flip-flops).
Precompiled on transistor level. Vol gt100k Full
Custom Transistor level design. Used for analog
circuits. SoC System on Chip. Processors and
logic on chip.
FPLD Field Programmable Logic Device. FPGA
Field Programmable Gate Array. gt1 milj gates! PLD
Programmable Logic Device CPLD Complex PLD.
lt10k gates SoPC System on Programmable Chip
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ASIC Design Phases
Design

• From idea to synthesizable model
• From synthesizable model ? masks ?Wafer
  fabrication
• To check the fabricated chip
• Slicing of wafer into separate chips ?wire
  bonding ? packaging

Fabrication
Testing
Packaging
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ASIC Design Phase
Design
Synthesis and Optimization
Fabrication
Netlist
Validation
Place RouteSimulations
Testing
GDS-II tape
Mask set(Photo masks)
Packaging
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ASIC Fabrication Phase
Dia 4, 6, 8.. etcThickness 0.5 mm
Design
Silocon wafers
Fabrication
Semiconductors fabrication
Standard cell Full custom
Testing
Metal layers inter- connections
Only custom stage in Gate Array
Packaging
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ASIC Fabrication Phase
Design
Fabrication
Test vectors
Wafer tests(Probing of pads)
Testing
Test equipment
Connection pads
Packaging
Chip
Wafer
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ASIC Fabrication Phase
Design
Scribing(Cutting wafers to chips)
chip
Fabrication
Bonding e.g. wire bonding to lead frame
Testing
Plastic moulding or ceramic packaging
Packagingand test
Test of circuits
Test vectors
43
n-MOS transistor basics
Gate oxide
Source
Drain
Gate
Positive voltage on the gate will result in a
channel of electrons below the gate oxide
(inversion gt majority carriers will be replaced
with minority carriers).
- - - - - - - - - - - - - - - - - - - - - - - -
p
n
n
Channel (minority carrierse-)
44
p_MOS transistor basics
Gate oxide
Source
Drain
Gate
Negative voltage (relative source) on the gate
will result in a channel of holes below the gate
oxide (inversion gt majority carriers will be
replaced with minority carriers).
p
p
p
n-well n
p
p

45
ASIC Fabrication PhasesLithography
Si - substrate
Si-oxide
Si - substrate
Photo resistOrganic polymer. Positive photo
resistsoluble after exposure with UV-light
(shorter and shorter wavelengths required)
photo resist
Si - substrate
UV -light
Glass photo mask
Si - substrate
Si - substrate
etching
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n-channel MOSFET
SiO2
Si-substrate
Etching
Doping(diffusion / Ion implantation)
Si-substrate
n
n
Poly silicon
SiO2
metal connectors
Thin oxide
Si-substrate
Si-substrate
n
n
SiO2
Si-substrate
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CMOS inverter
in
48
CMOS inverter
Vout
Vin
49
CMOS inverter
50
CMOS circuits
NAND gate
P
P
N
N
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VLSI words

• 0.25 micron process, 0.13 micron process, 0.09
  micron processsmallest dimension in a
  transistor is 0.25 micro meter etc
• Cu- layers. Copper is used for the metal layers
  gt lower resistance in the signal wires. 9 metal
  layers is not unusual!
• 6 inch wafer, 8 inch wafer Diameter is 6 inches,
  8 inches (newest).
• NRE (Non Recurring Engineering costs. Includes
  e.g. mask set costs. NRE increases with new
  (smaller) technology

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NRE cost evaluation

• Typical cost for an ASIC in 0.18 ?m is 5
  millions, in 0.13 ?m 10 millions. Future 0.45 ?m
  will cost more than 15 millions.
• Only Asics in very high volumes possible (gt100k,
  gt1000k)
• Possible solutions to ASIC cost problem
• Structured ASIC Modern Gate Array (GA) with
  more complex building blocks than traditionally
  GAs.
• Converted FPGA to Hardwired FPGA gt faster,
  cheaperhttp//www.altera.com/products/software/pl
  d/products/q2/qts-index.html?xyqts-gif

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ARCHITECTURE behav OF tb_exempel IS component
tt_buffer is port(rd in std_logic
out_buffer inout std_logic_vector(7 downto
0)) end component signal rd std_logic
signal out_buffer std_logic_vector(7 downto
0) BEGIN u1 tt_buffer port map
(rd,out_buffer) process begin
rdlt'1' wait for 500 ns rdlt'0'
wait end process process begin wait
for 1 us out_bufferlt"10101010" wait
end process END behav
VHDL Test bench problem
- tb_exempel -- joal 2003-10-07 -- Abstract To
demonstrate how multiple drivers can be --
generated in a test bench and -- how to avoid
problems with that LIBRARY ieee USE
ieee.std_logic_1164.ALL USE ieee.std_logic_arith.
ALL --
LIBRARY ieee USE ieee.std_logic_1164.ALL
USE ieee.std_logic_arith.ALL ENTITY tb_exempel
IS END tb_exempel
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ARCHITECTURE behav OF tb_exempel IS component
tt_buffer is port(rd in std_logic
out_buffer inout std_logic_vector(7 downto
0)) end component signal rd std_logic
signal out_buffer std_logic_vector(7 downto
0) BEGIN u1 tt_buffer port map
(rd,out_buffer) process begin
rdlt'1' wait for 500 ns rdlt'0'
wait end process process begin --
out_buffer driver in this process must have a
start value otherwise U is used and can't be
resolved!!!!
out_bufferlt"ZZZZZZZZ" wait for 1 us
out_bufferlt"10101010" wait end
process END behav
VHDL Test bench problem
- tb_exempel -- joal 2003-10-07 -- Abstract To
demonstrate how multiple drivers can be --
generated in a test bench and -- how to avoid
problems with that LIBRARY ieee USE
ieee.std_logic_1164.ALL USE ieee.std_logic_arith.
ALL --
LIBRARY ieee USE ieee.std_logic_1164.ALL
USE ieee.std_logic_arith.ALL ENTITY tb_exempel
IS END tb_exempel
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VHDL Test bench problem
Before code corrected
rd
out_buffer
UUUUUUUU
10101010
After code corrected
rd
out_buffer
01010101
10101010
1 ms
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IEEE 1076.1-1999 /VHDL-AMS, Analog modeling added
http//www.eda.org/vhdl-ams/
--------------------------------------------------
-------------------- -- The capacitor definition
begins..... --------------------------------------
-------------------------------- -- Schematic of
the capacitor component -- -- Ta1
o--------o Tb1 -- ------------------------------
---------------------------------------- LIBRARY
DISCIPLINES
USE DISCIPLINES.ELECTROMAGNETIC_SYST
EM.ALL ENTITY Capacitance
IS GENERIC (val REAL) PORT
(TERMINAL p,m ELECTRICAL) END

ARCHITECTURE behav OF Capacitance IS
QUANTITY u_c ACROSS i_c THROUGH p TO m BEGIN
i_cval u_c'dot END
57
VHDL-AMS, Analog modeling added