Status of CSC Trigger

1
Status of the Next Generation CSC
Track-Finder D.Acosta University of Florida
2
Track-Finder Crate Tests

• Last Fall we successfully tested a complete
  chain of prototypes, yielding perfect agreement
  with the simulation for millions of events
• Documented in TDR, with detailed Note to follow

SP
SR
CCB
MPC
Bit3 VME Interface
Custom backplane
100m optical fibers
3
A Compact Muon Trigger

• The next step is to reduce the CSC latency by
  consolidating several boards and chips and by
  increasing the clock frequency to 80 MHz
• New 1.6 Gbit optical link technology
• Texas Instruments TLK2501 80 MHz serializer
  new optics
• Reduces connections from peripheral crate (1? /
  link) so that all receivers can fit onto one
  board
• Synchronous pipelined SRAM
• Samsung, IDT
• Allows LUTs on Sector Receiver to operate at ?80
  MHz in order to reduce chip count
• High Density FPGAs
• 2.5M gates with Xilinx Virtex XCV2000E
• Fits all 17 FPGAs LUTs of Sector Processor
  into one chip
• Thus, the entire CSC Track-Finder can fit into 1
  crate

4
Possible Crate Layout
15
5
Possible Board Layout
6
SR/SP Inputs

• Muon Port Cards deliver 15 track stubs each BX
  via optical
• DT Track-Finder delivers 2 track stubs each BX
  via LVDS

Delivers 240 bits _at_ 80 MHz
7
SR/SP Outputs

• 6 track stubs are delivered to DT Track-Finder
  each BX via LVDS (can we multiplex at 80 MHz to
  save connector space?)
• 3 muons per SP are delivered to Muon Sorter via
  GTLP backplane

8
SR Memory Scheme

• Use cascaded synchronous SRAM to accomplish
  transformation of LCT bit patterns into global
  tracking variables
• Includes alignment corrections
• Multiplex muons _at_ 80 MHz to reduce chip count to
  45

9
Pipelined Memory Tests

• Developed small evaluation board to test two
  pipelined memories in series
• Samsung 1M x 18 synch. SRAM (K7A161800M)
• Include scheme to multiplex two muon stubs
  through same memory set _at_ 80 MHz
• Tested chips up to 150 MHz and encountered no
  errors with random number inputs
• Specified maximum frequency is 180 MHz
• Low power
• 1W per memory at 150 MHz
• Latency determination
• 2 clocks per memory (4 clocks for two in series)
• 7 clocks total including 80 MHz serialization
  and de-serialization of muon stubs ? 3.5 BX _at_
  80 MHz
• May be possible to shave 0.5 BX

10
SR Memory Prototype
Tested hardware
Simulation illustrating clocking of board
11
SR Latency Estimate _at_ 80 MHz

• Optical links (T.I.)
• 76 82 ns latency for serialization and
  de-serialization of one frame, 0.5 BX to wait
  for second frame of data
• Therefore, 2 BX for receiving complete muon
  stub in SR (was 2 BX for HP Glink as well)
• Track stub conversion
• 3.5 BX (was 2 BX in last prototype ? 1.5 BX)
• Includes track stub serialization/de-serializatio
  n _at_ 80 MHz and propagation through two memories
• Total latency is 5.5 BX
• Compare to 4 BX of last prototype ? 1.5 BX
• However, this estimate is conservative
• Possible to process track stub data off optical
  link without waiting for second frame
• Saves 0.5 BX 1 BX by not waiting removing
  some logic
• Judicious choice of data in first frame of
  optical link, and new LUT scheme
• Could run clock for synch. SRAM at 120 or 160
  MHz

12
SP in a Chip Study

• Feasibility study was performed to fit all Sector
  Processor logic into one FPGA
• Merged all separate schematics from current SP
  prototype into one project (17 FPGAs)
• Transformed large Track Assembler LUTs into a
  Verilog algorithm for FPGA
• Utilized 63 of the resources of a Xilinx
  Virtex-E (XCV1600EFG680-8)
• Simulation shows that the latency of the SP
  logic is 11 BX at a maximum frequency of 41 MHz
• Add 1 BX for final PT Assignment LUT
• Compare to 15 BX of current SP prototype ? save
  3 BX
• ChannelLink between SR and SP removed (save 4
  BX more)
• Improvement to total SRSP latency ? save at
  least 5.5 BX
• SP Chip I/O
• 300 input bits (80 MHz)
• 100 output bits (40 MHz)

13
Backplane Development

• First CSC TF backplane technology was
  ChannelLink
• It worked ! Serialization reduced 600 signals
  into 200 for SP
• Latency is long 4 clocks
• Next generation backplane technology will be GTLP
• No differential signals (fewer traces)
• We have tested a small prototype backplane with
  GTLP signals
• It works tested drivers from Fairchild, and
  Xilinx Virtex I/O
• We have developed and produced a full 21 slot
  custom VME backplane for use in the CSC front-end
  peripheral crate
• Includes 40 MHz bussed signals and 80 MHz
  point-to-point
• Highest density is 660 signals into Muon Port
  Card(vs. 680 signals into CSC Muon Sorter in
  CSC TF crate) multiplexed at 80 MHz
• Have tested bussed signals with backplane fully
  loaded ?

14
Prototype Peripheral Crate Backplane
15
Schedule Plans

• The merged Sector Receiver/Sector Processor
  concept looks feasible and saves latency
• Approximately 5.5 BX savings so far, work
  continuing
• All RD successful
• New optical links, new synch SRAM, SP-on-a-chip,
  GTLP backplane
• Single crate Track-Finder is simpler to maintain
• Proposal is to develop a new prototype by late
  summer 2002
• Possible use for integration tests with DT
  Track-Finder?
• Possible use for structured beam tests?
• Need to define a DAQ interface for readout
• Slow control monitoring is presumably through VME