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Chapter 7 High-Speed Signal

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Chapter 7 High-Speed Signal Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe_at_ee.ucla.edu – PowerPoint PPT presentation

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Title: Chapter 7 High-Speed Signal


1
Chapter 7 High-Speed Signal
  • Prof. Lei He
  • Electrical Engineering Department
  • University of California, Los Angeles
  • URL eda.ee.ucla.edu
  • Email lhe_at_ee.ucla.edu

2
High-speed Links are Everywhere
Backbone Router Rack
PC or Console
SredojevicICCAD08
3
High-Speed Links Applications
  • Chip-to-chip signaling
  • Computers, games SDRAM(DDR, DDR2) 100-700MHZ,
    RDRAM 800-1600MHz, DDR3 800-1600MHz, DDR4
    1.6-3.2GHz, XDR DRAM 3.2-6.4GHz
  • Board-to-board
  • Computers Peripherals- PCI (66-133-400MHz), PCIe
    (250M-500M-1GHz), Infiniband (2.5Gb/s)
  • Networks
  • LAN Fast Ethernet, Gigabit Ethernet, 10G
    Ethernet
  • WAN OC-12 (625MHz), OC-192(12.5GHz)
  • Routers 625Mb/s 2.5Gb/s

4
Outline
  • Link Design Basics
  • Signal Integrity
  • High Speed Signaling Architectures
  • Equalization
  • Post-Silicon Tuning of High-Speed Signaling

5
Noise
  • Signals may be corrupted from many sources
  • Inter-symbol interference (ISI)
  • Frequency-dependent attenuation (dispersion)
  • Reflection
  • Oscillation
  • Crosstalk
  • Power supply noise
  • Real noise
  • Thermal and shot noise
  • Parameter variation
  • Noise measure
  • Eye diagram
  • Timing jitter
  • Amplitude noise

6
Inter-Symbol Interference
  • A signal interfering with itself
  • Ideally a transmission system is time invariant
  • No history of previous bits
  • In reality, the state of the system is affected
    by previous bits
  • Signals that dont reach the rails by the end of
    cycle
  • Signals transition time is limited by channel
    bandwidth
  • Reflections on the transmission lines
  • Magnitude and phase of excited resonances

7
ISI - Dispersion
  • Frequency-dependent attenuation
  • In general, channel is low pass
  • Our nice short pulse gets spread out
  • Example a 101 pattern

8
ISI - Reflection
  • Reflections of previous bits travel up and down
    transmission lines
  • A mismatch of d gives (to the first order) a
    reflection of ?

9
ISI - Resonances
  • Oscillations are excited by signal transitions
    and may interfere with later transitions
  • Excitation of resonant circuits is reduced with
    longer transition times
  • Slower edge has less high frequency spectral
    content
  • Resistance damps oscillation

10
Crosstalk
  • Crosstalk is the coupling of energy from one line
    to another via
  • Mutual capacitance (electric field)
  • Mutual inductance (magnetic field)
  • One signal interfering with another signal

Mutual Inductance, Lm
Mutual Capacitance, Cm
Zo
Zo
Zo
Zo
far
far
Cm
Lm
near
Zs
near
Zs
Zo
Zo
11
Crosstalk Induced Noise
  • The mutual inductance will induce current on the
    victim line opposite of the driving current
    (Lenzs Law)
  • The mutual capacitance will pass current through
    the mutual capacitance that flows in both
    directions on the victim line

Zo
Zo
Zo
Zo
far
far
ICm
ILm
Lm
near
Zs
near
Zs
Zo
Zo
12
Voltage Profile of Coupled Noise
  • Near end crosstalk is always positive
  • Currents from Lm and Cm always add and flow into
    the node
  • For PCBs, the far end crosstalk is usually
    negative
  • Current due to Lm larger than current due to Cm
  • Note that far and crosstalk can be positive

Zo
Zo
Far End
Driven Line
Un-driven Line victim
Zs
Near End
Driver
Zo
13
Power Supply Noise
  • The power supply network has parasitic elements
  • On-chip resistive
  • Off-chip inductive
  • Current draw across these elements induces a
    noise voltage
  • Instantaneous current is what matters
  • May be many times the DC current
  • 10W chip draws 4A at 2.5V
  • Peak current may be 10-20A

14
Simultaneous Switching Outputs (SSO)
  • When several outputs switch simultaneously,
    significant current is drawn from the supply or
    sent into ground
  • Supply connections have inductance
  • SSO currents produce a voltage drop across these
    inductances
  • On-chip, the VDD to VSS voltage difference
    decreases
  • Effect grows with number of drivers switching
  • Quadratic with the inverse of transition time
  • Between chips, the drops across VSS inductances
    can effect driver timing and shift the receiver
    threshold

15
Other Noise Sources
  • Alpha particles
  • 5MeV particle injects 730fC of charge into
    substrate
  • One node typically collects less than 50fC
  • Thermal and shot noise
  • Proportional to bandwidth typically in the uV
  • Parameter mismatch
  • VT and ß have deviation proportional to
    1/sqrt(WL)
  • Systematic variations depend on layout

16
Eye Diagram
This is a 1
This is a 0
Eye space between 1 and 0
With voltage noise
With timing noise
With both!!
17
Eye Diagram (contd)
  • Standard measure for signaling
  • Synchronized superposition of all possible
    realizations of the signal viewed within a
    particular interval
  • Timing jitter
  • Deviation of the zero-crossing from its ideal
    occurrence time
  • Amplitude noise
  • Set by signal-to-noise ratio (SNR)
  • The amount of noise at the sampling time

18
Outline
  • Link Design Basics
  • Signal Integrity
  • High Speed Signaling Architectures
  • Equalization
  • Post-Silicon Tuning of High-Speed Signaling

19
Signaling Main Idea
  • A good signaling system isolates the signal from
    noise rather than trying to overpower the noise
  • Crosstalk
  • Terminate both ends, use homogeneous media
  • ISI
  • Matched terminations, no resonators, rise-time
    control
  • Power supply noise
  • Avoid coupling into signal or reference
  • Differential signaling
  • Current mode
  • stable reference

20
Architecture of Signaling
21
Signaling Architecture Tradeoffs
  • Signal modulation
  • PAM (Pulse-amplitude modulation)
  • Pulsed (Return-to-Zero, RZ) signaling
  • Binary (exNRZ) or Multiple-level signaling (MLS)
  • Uni-directional or Bidirectional
  • Time-multiplexed bidirectional or simultaneous
    bidir.
  • Single-ended or differential
  • Current mode or voltage mode
  • Bus or single-trace
  • Point-to-point or multi-drop

22
Example System - Trade-offs
23
Voltage Mode vs Current Mode
  • Main differences are
  • Ease of control and generation
  • Much easier to generate a small current than a
    small voltage
  • Coupling of supply noise
  • 50 of supply noise shows up on the data line in
    the matched voltage mode potentially much less
    in a high-Z current-mode driver
  • Generation of high-Z switches easier than
    controlled-Z switches

24
Single-ended vs Differential
  • Single-ended signaling
  • compare to shared reference
  • Often used with a bus
  • Issues
  • Generates SSO noise
  • How to make reference
  • How to quiet reference
  • Crosstalk cannot be made common-mode
  • Differential signaling
  • compare between two lines
  • Noise immunity
  • Many noise sources become common mode
  • Issues
  • Differential must run gt 2x as fast as
    single-ended to make sense
  • Otherwise, powerx2, pinsx2

25
Binary vs Multiple-level (4-PAM)
  • 4-PAM uses 4-levels to send 2 bits per symbol
  • Each level has 2 bit value
  • Binary (NRZ) is 2-PAM
  • Use 2-levels to send one-bit per symbol

26
When Does 4-PAM Make Sense?
27
Simultaneous Bidirectional Signaling
  • Wires can transmit waves in both directions
  • It seems a shame to only use one direction at a
    time
  • Simultaneous Bidirectional Signaling
  • Transmit waves in both directions at the same
    time
  • Waveform on wire is superposition of forward and
    reverse traveling wave
  • Subtract transmitted wave at each end to recover
    received wave
  • There are 3-levels on the line but its still
    2-level signaling
  • Much more sensitive to reflections and crosstalk

28
Outline
  • Link Design Basics
  • Signal Integrity
  • High Speed Signaling Architectures
  • Equalization
  • Post-Silicon Tuning of High-Speed Signaling

29
Equalization
equalizer
channel
  • Channel is band-limited, most of them are
    low-pass
  • Goal is to flatten the overall response
  • Equalization Boost higher frequencies relative
    to lower frequencies
  • Can be done at Tx or RX or both

30
Receiver Linear Equalizer
  • Amplifies high-frequencies attenuated by the
    channel
  • Pre-decision
  • Digital or Analog FIR filter
  • Issues
  • Also amplifies noise!
  • Precision
  • Tuning delays (if analog)
  • Setting coefficients (adaptive filter)
  • Adaptive algorithms such as LMS

31
Transmitter Linear Equalizer
  • Tx Pre-emphasis Filter
  • Attenuates low-frequencies
  • Need to be careful about output amplitude -
    limited output power
  • If you could make bigger swings, you would
  • EQ really attenuates low-frequencies to match
    high frequencies
  • Also FIR filter D/A converter
  • Can get better precision than RX
  • Issues
  • How to set EQ weights?
  • Doesnt help loss at high f

32
Tx Linear EQ Single Bit Response
33
Outline
  • Link Design Basics
  • Signal Integrity
  • High Speed Signaling Architectures
  • Equalization
  • Post-Silicon Tuning of High-Speed Signaling

34
Process Variation vs Analog Circuits
ITRS
  • Threshold voltage variation is increasingly
    dominant and is primarily random
  • Due to increasing and random doping fluctuation
  • Corner-based design is not effective for match
    used widely in analog circuits
  • Often results in over-sized circuits and
    excessive area/power

35
Post-Silicon Tuning is Effective
LiICCAD08
  • Post-silicon tuning is effective to compensate
    random process variation
  • Digitally tunable circuit is commonly adopted
  • Insensitivity to noise and variation
  • Suitable for process migration

36
Post-Silicon Tuning of High-Speed Signaling
  • Algorithm Framework
  • Problem formulation
  • Branch and bound based algorithm
  • Case Study I Transmitter
  • Case Study II PLL
  • Conclusions

37
Unit Cell Based Design Methodology
  • Pre-characterize different types of unit cell,
    e.g., transistor with a given threshold voltage
    and unit W/L.
  • A transistor of larger W/L can be synthesized by
    connecting those unit cells of same type in
    parallel
  • Design variables simply become
  • type of unit cell a(threshold)
  • number of unit cells in parallel (sizing)
  • Constraints such as output swing is satisfied for
    correct operation
  • Apply to other circuit elements such as unit
    capacitance and resistance
  • Make design better and modeling more accurate

38
Digitally Tunable Circuits
one tap in a pre-emphasis filter
current source can be implemented by
current-division DAC
  • Current-division DAC is commonly used to combat
    process variation
  • Two tuning parameters
  • LSB size ( ) minimum step during
    digital-to-analog conversion
  • Resolution (ß) number of bits used

39
Impact of Post-Silicon Tuning
(a) Without Tuning
(b) With Tuning
  • Example BER for a high-speed link
  • 4-tap pre-emphasis filter in a transmitter
  • 0 (3s) variation in Vt
  • Design-time optimization and post-silicon tuning
    circuit both need area, and joint optimization is
    must

40
Joint Optimization
parametric yield
power constraint. Process variation changes power
area constraint. Process variation does not
change layout area
bound on design parameters
bound on the total number of unit cells types
bound on the LBS and resolution
e
41
Optimization Challenges
  • 3000 Monte Carlo runs over different unit cell
    design a, resolution ß, and LSB size for one tap
    of FIR
  • Discrete problem with non-convex objective and
    constraints
  • Solution space surface is rough and many local
    maxima exist
  • Significant improvement can be expected

42
Overall Algorithm
  • Algorithm framework
  • Partition the solution space by LSB size ( ) and
    unit cell type (a)
  • Develop a bound on the parametric yield
  • Discard (fathom) if bound worse than the current
    best solution
  • Use gradient ascent method to find the local
    maxima
  • Sequentially take steps in the direction
    proportional to the gradient.
  • Bound estimation
  • Remove the area and power constraints
  • Use LMS algorithm to find optimal yield value

43
Gradient Ascend Method
  • In each un-pruned region, sequentially take steps
    in direction proportional to the gradient, until
    a local maximum of the objective function is
    reached.
  • At each step, increase/decrease each variable by
    1 in turn and check the change of the objective
    function.
  • Always take the change (direction) that causes
    the maximum increase.
  • Termination of the algorithm indicates that one
    of the local maxima has been reached or that we
    have reached the boundary.
  • The initial guess for the GDA can be arbitrarily
    chosen. In our experiments, we find that it did
    not influence runtime or quality significantly.
  • We also observed that the algorithm always
    converges to local optimum within two or three
    iterations.

44
Post-Silicon Tuning of High-Speed Signaling
  • Algorithm Framework
  • Case study 1 transmitter
  • Knobs for design-time and post-silicon
  • Modeling and formulation
  • Experimental results
  • Case Study 2 PLL
  • Conclusions

45
Knobs for Optimization
  • Given transmission channel ? filter coefficient ?
    transistor size
  • change channel behavior ?
    parasitic capacitance

46
Knobs for Optimization
47
Problem Formulation
  • For transmitter
  • ,

random variable
48
BER Distribution Comparison
  • 20 (3s) variation in Vth with 10000 Monte Carlo
    runs
  • Design 1 - without tuning circuit
  • All resources are used for filter
  • Unavoidable large variation
  • Design 2 - one tap filter
  • All resources are used for DAC
  • Has extreme small variance but suffers severe ISI
  • Design 3 heuristic design
  • Assume 4-tap filter
  • Assume LSB size is equal for each tap
  • Limit the solution space
  • Good improvement compared to two extreme cases
  • Design 4 - our algorithm
  • Provides better solution (mean, variance)

49
Yield Rate
  • Experiment setting
  • Channel 30cm differential microstrip line with
    FR-4 substrate
  • 5GHz data rate
  • Yield is set by BER1e-15 (estimated by EVM)
  • Yield comparison for different area constraints
  • Our algorithm always provide better yield than
    design heuristic
  • With aggressive area constraint, our algorithm
    has much less yield degradation
  • Saturation effect
  • Up to 47 improvement

area
50
Yield with Power Constraint
vt variation
power
51
Post-Silicon Tuning of High-Speed Signaling
  • Algorithm Framework
  • Case study 1 Transmitter
  • Case study 2 PLL Design
  • Conclusions

52
Jitter Modeling
  • PLL output clock jitter
  • Hnin and HnVCO are the noise transfer function of
    reference clock noise and VCO noise
  • E.g.
  • Tunable PLL
  • Jitter can be changed by tuning the charge pump
    current ratio

MansuriJSSC02
53
Joint Optimization
  • Design-time optimization
  • Two charge pumps Icp1, Icp2
  • Ratio (Icp1/ Icp2) determines output RMS jitter
  • Optimal ratio can be found using design-time
    optimization
  • Again, process variation would cause performance
    degradation
  • Digitally tuned current mirror
  • Small reference current
  • Consumes less power
  • ? need to be far less than unity
  • Limited tuning resolution
  • Large reference current
  • Good tunability
  • Power and area penalty

HorowitzJSSC00
54
Same Formulation Applies
  • For PLL
  • objective function becomes
  • and area can be computed in a way similar
    to the transmitter case.

55
Experimental Results
  • PLL with digitally controlled charge pump current
  • Yield is defined by output clock RMS jitter
  • Design heuristic using minimized biasing current
  • Consider 30 Vth variation

Improve the yield by up to 56
56
Conclusions
  • Formulate a joint optimization problem for
    digitally tuned analog circuits
  • Consider both design-time optimization and
    post-silicon tuning
  • Maximize performance yield s.t. power and area
    constraints
  • Propose a general optimization framework
  • Combine branch-and-bound and gradient-ascent
    algorithm
  • Effectively find the global optimum
  • Two joint optimization design examples for
    high-speed serial link
  • Transmitter design
  • PLL design
  • Experiments show great (gt47) yield improvement
    over common circuit design heuristic
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