# ECE 551 - Digital System Design - PowerPoint PPT Presentation

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## ECE 551 - Digital System Design

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### ECE 551 - Digital System Design & Synthesis Lecture 2 - Pragmatic Design Issues Part 2 Overview Miscellaneous problems that arise in design and their solutions – PowerPoint PPT presentation

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Title: ECE 551 - Digital System Design

1
ECE 551 - Digital System Design Synthesis
Lecture 2 - Pragmatic Design Issues Part 2
• Overview
• Miscellaneous problems that arise in design and
their solutions
• Issues considered in this part
• Asynchronous Circuits
• Clock Design and Delays
• Electrical Issues

2
Asynchronous Circuits
• Delay-dependent design
• Combinational hazards
• Level/pulse conversion
• Synchronization
• Memory timing

3
Delay-Dependent Design
A
DA
A
DA
4
Combinational Hazards
• Hazard in a Multiplexer

A
1
B
F
C
1
B
F
5
Combinational Hazards (continued)
• Classification of Combinational Hazards
• Static
• Dynamic
• Essential
• Consequences of Hazards
• Signals with hazards in or entering asynchronous
environments
• Hazard Prevention
• Redundant Logic
• Delay Control

6
Level/Pulse Conversion
DATA_IN
DATA_OUT
Clock
• Level on DATA_IN must be longer than a clock
period and must not rise close to the positive
clock edge. Ideally synchronous with the Clock.

7
Synchronization
D
Q
Clock
C
Clock
Req
Rep
• Asynchronous Rep can cause sequential circuit
malfunction since it reaches two or more
flip-flops.
• Solution Put synchronizer (PET DFF) in Rep path.

8
Metastability
• A specific phenomena that in the present of
certain closely timed events on the inputs can
cause bizarre latch and flip-flop behavior
• Hanging for a time at a threshold level
• Produce a damped oscillation
• One remedy Use two to three synchronizers in
series

9
Memory Timing
• Many memories are asynchronous circuits, e. g.,
SRAMs are latch-based without a clock on the
latch
• Their inputs can respond to glitches such as
hazards.
• A majority of all memory inputs need to be
glitch-free.
• Since memories involve capture of data in
times apply to many of the inputs, notably the
• Memory outputs often involve 3-state buses one
must be sure that the bus is active whenever data
• When designing with memories, careful attention
must be given to meeting fully all of the timing
specifications.

10
Asynchronous Design
• Using classical techniques, because of the
difficulty of eliminating the hazards, very
difficult to insure correct operation under all
timing possibilities
• Therefore, dont do it!
• If you truly need it, investigate some of the
more contemporary approaches which avoid some of
the many difficulty.

11
Clocking Design
• Clock skew
• Clock gating
• Clock jitter
• Clock buffers
• Interconnect delay control

12
Clock Skew
• Clock skew is the arrival of the active clock
edge(s) at different times in different parts of
a chip or system.
• Clock skew can result from
• logic delays, as in clock gating and buffering
• interconnection delays.
• Clock skew can cause
• Premature capture of new state values
• The shortening of the effective allowable delay
along a path from flip-flop to flip-flop
• Lengthening of the effective allowable delay
along a path from flip-flop to flip-flop

13
Clock Gating
• Use of gate logic to interrupt the clock signal
to a portion of the logic to prevent the state
from changing
• Why use it?
• Simplifies logic
• Reduces power consumption
• Why not use it?
• Can circuit failure due to clock skew
• Complicates circuit testing

14
Clock Jitter
• Clock does not provide a signal having a fixed
frequency. Clock period is
• slightly shorter, or
• slightly longer
• on any given cycle.
• The clock jitter is the absolute value of the
maximum difference between
• the nominal period, and
• the shortest and the longest clock periods
• Can be very serious if circuit has multiple
clocks with independent jitter.

15
Combinational Logic Delay Upper Bound
• Components of the Bounds
• Nominal Clock Period CP
• FF Propagation Delay tFF
• FF Set-up Time tSU
• Clock skew (of destination FF clock with respect
to source FF clock) ( or ) tsc
• Clock Jitter Magnitude tCJ
• Combinational Logic Delay Upper Bound along
Particular FF to FF path
• DCL lt CP tsc tCJ tFF tSU
• From this equation, we see that
• Clock skew may either degrade (if negative) or
enhance (if positive) performance!

16
Combinational Logic Delay Lower Bound
• Related to incorrect function due to hold time
violation
• Left as an exercise

17
Clock Buffers
• Reasons for buffering
• Long clock interconnects
• Must be designed to minimize skew
• Overall, clock distribution in an aggressive
design is a major separate task

18
Interconnect Delay Control
• Interconnect delay (exclusive of clocks) for
global interconnects is a significant component
of the FF to FF delay in submicron channel length
circuits.
• Implication Interconnect delay has a significant
impact on performance in submicron channel length
designs.
• Ideally global routes are from FF to FF.
• If combinational logic involved, all interconnect
delay subtracted from combinational logic delay
upper bound

19
Interconnect Delay Control (continued)
• Methods of handling interconnect delay
• Chip floorplanning to reduce global routing
• Interconnect driver strength and inserted buffers
• Interconnect sizing
• Circuit retiming (if combinational logic in
series with global interconnect)
• Last resort addition of FFs to very troublesome
paths and redesign of parts of system affected.

20
Electrical Issues
• Constant inputs
• Slew rate and ground bounce

21
affect
• Output levels
• Local Power Dissipation
• Delay
• Consider two logic families assuming both loads
and drivers are in the families
• TTL
• CMOS

22
• TTL (Transistor-Transistor Logic) is a current
sinking technology.
• For driven TTL gates, at LOW, a substantial
current flows out of inputs into the driving
output.
• The static current for the driving gate at LOW
• IC VCC /(RC RB/FO)
• where RC is the output resistance of the TTL
driver transistor in saturation, RB is the
resistance in the driven gates governing the
input current, and FO is the fanout in terms of
number of gates driven.

23
• As FO increases, the current increases which
increases
• the LOW output level
• the power dissipation
capacitance driven which increases delay.
• The increase in the low level can cause noise
problems.
• The increase in power dissipation can cause
thermal problems and possible IC damage.

24
• The current into or out of a CMOS gate output
flows only during transitions and is otherwise
negligible.
• Increased fanout FO increases the capacitive load
on the driving gate which increases
• the delay of a transition
• the duration of time during which a sizable
current flows into or out of the driving gate.
• If the output changes frequently, then the
dynamic current could cause power dissipation to
produce a local thermal problem and possible IC
damage.

25
Constant Inputs
• If a constant input is to be applied to an IC
from outside, it is generally a good idea to
include a resistance between the ground or supply
and the input for the following reasons
• prevents a large current at the input for some
technologies at power-up that can cause damage or
disable the IC.
• allows the fixed signal to be changed during
testing.

26
Slew Rate and Ground Bounce
• If large dynamic currents are drawn from the
power supply, there can be significant changes in
the GND or VCC voltage values on chip due to lead
inductance.
• This phenomena is called ground bounce in the
case of the ground voltage.
• The high current problem most often arises with
output buffers driving large off-chip
capacitances.

27
Slew Rate and Ground Bounce Remedies
• The voltage transient is related to
• L dI/dt where I is the power or ground current.
• Reduce the effective lead inductance L by using
• It is not uncommon for a significant percentage
of all leads on an IC to be supply or ground
• Reduce dI/dt by reducing the slew rate, the rate
of change in the output voltage.
• By reducing C dV/dt, the current and its
derivative are reduced.

28
Summary
• Design Issues
• Three-State and Other Hi-Z States
• Sequential Circuit Basics
• Asynchronous Circuits
• Clock Design
• Electrical Issues
• All are important
• Far from exhaustive

29
References
• Seidensticker, Robert B., The Well-Tempered