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Invited Tutorial: Analog

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Title: Invited Tutorial: Analog


1
Invited Tutorial Analog Mixed Signal
Verification
  • Kevin D Jones
  • kdj_at_acm.org

2
An Apology
  • I owe you (collectively) an apology!
  • Paper accompanying this talk is not in
    proceedings
  • Kevin D. Jones
  • Rambus Inc.

3
Overview
  • Audience Calibration
  • Digital and Analog
  • The Analog Design ( Verification) Process
  • Mixed mode Design ( Verification) Process
  • Formal Verification of A(MS) Systems
  • An Analog Example
  • The State of the Art
  • A Mixed Mode Example
  • Open Problems - A Challenge
  • Summary and Conclusions

4
Audience Calibration
  • Think about what you see in the following picture

5
If you saw this
Digital world view - An approximation of a 0 to 1
transition
6
If you saw this
Analog world view - An approximation of a linear
transfer function
7
If you saw this
OUT tanh(IN)?
Theory world view - A representation of the
hyperbolic tangent function
High class analog world view
8
Digital and Analog
  • Different worlds
  • Think differently
  • Different mindset, tools, approaches
  • Occasionally forced to coexist in mixed signal
    designs
  • My assumptions for this audience
  • People understand digital design and
    verification
  • Analog is the novel part
  • Main focus on the front end

9
Digital Circuits
  • Verify this two-input AND gate

10
Digital Abstraction
1
0
0
0
  • States are discrete and countable
  • Must verify the properties at all states

11
Digital Verification
  • Practice today (Exhaustive) Simulation
  • Directed pseudo-random simulation
  • Coverage based
  • Formal methods
  • BDD based exhaustive state analysis
  • Symbolic simulation
  • Tools Specman, SystemVerilog, Equivalence
    Checkers, Model Checkers, Theorem Provers,
  • Quite tractable for Formal Methods and lots of
    research has been done

12
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13
Aside AMS Verification is becoming a Significant
Problem
  • More and more systems have analog components
  • In recent DAC Keynote, Justin Ratner pointed out
    the world is fundamentally analog
  • Fast becoming a leading cause of SoC failure

14
Analog Design ( Verification) Process
15
Analog Design
  • Fundamentally schematic based
  • Draw the circuit
  • Very little abstraction
  • Not too many equations in practice
  • Theory and equations in school
  • Simulation in practice
  • Draw it, Spice it, Repeat

16
Analog Design Process
  • Identify circuit class
  • Pick a topology
  • Initial sizing
  • Simulation
  • Observe results
  • Repeat until acceptable
  • Verify

17
Topology
  • For the desired class of circuit
  • current mirror, amplifier, oscillator, PLL, ...
  • Go to the text book and pick the topology that
    you believe has the best possibility of meeting
    the critical specs
  • Topology means arrangement of fundamental
    components
  • transistors, capacitors, resistors

18
Sizing
  • The fundamental parameters for transistors are
    Width and Length
  • Physical dimensions effecting speed (delay),
    strength, power and load of the circuits
  • Initial sizing involves an educated guess as to
    the lengths and widths that will deliver the
    desired critical specification elements

19
Simulation
  • Unlike the digital world, simulation is a
    fundamental part of the design process
  • many parameters are unknown until after
    simulation
  • SPICE
  • DC-analysis
  • AC-analysis
  • Transient

20
Design Loop
  • Simulate
  • Eyeball (or measure) result
  • Tweak parameters
  • Repeat until results are acceptable for critical
    parameters
  • measure remaining parameters
  • Write spec

21
Aside Fancier Tools
  • Cadence Neocircuit
  • Automates the sizing loop
  • Reduces the human effort
  • Very expensive in terms of machine effort

22
End of Design Loop
  • A completed schematic
  • Essential parameters are shown to be in spec (for
    process parameters used for simulation)?

23
Verification of Analog Circuits
  • Transistor level models
  • Circuit simulator (Spice)?
  • DC simulation
  • AC simulation
  • Parameter sweeping
  • Statistical variation (Monte Carlo)?
  • Tools SPICE (HSPICE, PSPICE, Spectre, eldo, )?
  • Transient (time based) simulation is very
    expensive
  • Simulation inputs based on designers
    understanding/experience/intuition
  • i.e. verification is the same as design simulation

24
Verification
  • No real notion of verification as a separate
    process using different tools and approaches
  • Design is exercised not verified
  • Everything is based on simulation
  • Analog Verification today is roughly equivalent
    to Digital Verification in 1990

25
Statistical Verification
  • Monte Carlo simulation
  • simulators support statistical variation of
    certain input parameters
  • Hits some variant spaces
  • classical corners, random variation
  • Very expensive
  • Each simulation may take a long time
  • Overall result is as strong as the number of
    simulations

26
Mixed Mode
  • Real systems are always Mixed Mode or Mixed
    Signal
  • Some digital components
  • Some analog components
  • Communicating across boundary
  • One tool
  • AMS Simulator

27
Verification (should) ! Simulation
  • 25 Years of research in verification of digital
    systems has shown that simulation is not a
    sufficient tool for verification
  • For analog systems, this is even more true since
    (transient/time based) simulation is very
    expensive
  • Look for an abstraction that allows analysis

28
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29
AC Analysis is a Formal Method for Analog
  • AC analysis in SPICE provides the transfer
    function (TF)?
  • TF a complete description of the linear system
    in frequency domain
  • No further need to simulate circuits in transient
    simulation as long as the input signals remain
    small
  • The circuit is formally verified

30
Non-linear Domains
  • The formal techniques for analog circuits work
    very well in linear domains
  • Many (most) circuits are not linear in the
    voltage or current domains
  • PLLs are obviously very non-linear in V
  • All the simulator AC analysis tools work in V or
    I
  • This seems to imply they are not useful for most
    circuits!

31
Variable Domain Transformation
  • Most circuits are not linear in voltage or current
  • but are linear in some domain
  • phase, frequency, delay, duty-cycle,

32
Domain Translators
  • V?? Phase Detector and
  • ??????????????????????????????????????????????????
    ????V Phase Mixer
  • Must propagate perturbations correctly

33
Domain Transformation gives FV
  • Use domain translators to map the linear domain
    to V or I
  • Verilog-A is a good vehicle for developing
    translators
  • Perform analysis in this domain using AC analysis
    tools
  • Use inverse translator to map back to original
    linear domain for results
  • All the benefits of linearity together with all
    the benefits of V/I AC simulation techniques
  • A classic analog approach to Formal Verification

34
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35
Bugs in Analog/MS Systems
  • Parametric bugs
  • E.g. Jitter too high
  • The usual focus of designers effort
  • Requires better models and simulation techniques
    for improvement
  • Functional bugs
  • E.g. PLL doesnt lock!
  • Very difficult to find due to long simulation
    times and large spaces

36
An Example from the Real world
  • The example is extracted from an actual design
    failure
  • Some issues were only found in measurement of
    fabricated test chips
  • The design was validated as well as any analog
    designs are in practice today
  • The scale of the example is reduced to make it
    approachable from an academic perspective but all
    of the issues are still present

37
An Even Stage Ring Oscillator
  • Ring oscillators are a common component used in a
    variety of analog applications
  • The obvious design uses an odd number of inverter
    stages to produce oscillating 0 and 1 signals
    at a frequency dependent on the inverter delay
  • Even (2 or 4) stage oscillators are used when
    quadrature clocks are useful

38
The Complete Description
  • -------------------------------------------------
    ----------
  • Simulation netlist
  • -------------------------------------------------
    ----------
  • .
  • .param lp1.0u ln1.0u
  • .param wnbridge 2u wpbridge4u
  • Circuit ceases to oscillate above this ratio
  • .param ratioChainToBridge 1.972
  • Circuit ceases to oscillate below this ratio
  • .param ratioChainToBridge 0.31
  • .param wnchain 'wnbridgeratioChainToBridge'
  • .param wpchain 'wpbridgeratioChainToBridge'
  • .global vdd gnd
  • .subckt INV in out psource nsource
  • Mpullup out in psource vdd pch llp wwp
  • Mpulldown out in nsource gnd nch lln wwn
  • .ends INV
  • sring - a ring oscillator with bridges
  • -------------------------------------------------
    ----------
  • Libraries, parameters and models
  • -------------------------------------------------
    ----------
  • .protect
  • .lib '/user/cad/process/tsmc65/model/spice/g/v1.
    0/local/fets.lib' TT
  • .lib ./cln90g_lk.l TT
  • .unprotect
  • .model pch pmos
  • .model nch nmos
  • -------------------------------------------------
    ----------
  • Operating point
  • -------------------------------------------------
    ----------
  • .temp 30
  • .param supplyVoltage1.5V
  • -------------------------------------------------
    ----------
  • Initial conditions and stimuli
  • -------------------------------------------------
    ----------
  • .IC V(A2)'supplyVoltage1.'

39
Challenge for Formal Methods
  • The obvious digital abstraction doesnt hold
  • It has interesting failure modes
  • It is very sensitive to the exact sizing of the
    ring and bridge transistors
  • It has sensitivities to initial conditions for
    some sizes
  • The challenge Show that this circuit oscillates
    for all initial conditions for some sizing
  • Extra credit Show the sizing ratios regions for
    the ring and bridge transistors

40
Good
41
Bad
42
Ugly
43
Some Formal Approaches
  • The ESRO example has been tackled by a number of
    different groups
  • Methods used differ dramatically
  • Recent publication in FAC 08 and surrounding
    conferences
  • Following section gives an overview of a variety
    of approaches to this problem and some other
    noteworthy approaches on a similar scale

44
Stability analysis
  • UBC
  • Pencil and paper approach
  • Use monotonicity of fundamental components to
    find DC equilibria, VT derivative to analyse
    stability
  • Unstable gt no DC steady state gt no lock up
  • GLSVLSI 2008

45
iSpice
  • CBL
  • Formulate example as an SMT problem using
    arithmetic intervals as underlying theory
  • Proves properties based on DC, Transient and PSS
    simulations
  • Shows regions of stability
  • FAC 2008

46
Discrete Abstraction
  • University of Frankfurt
  • Divide continuous space into discrete regions for
    model checking
  • Analog specification language
  • DATE 08

47
Petri Net Models
  • University of Utah
  • Translating AMS circuits into LHPN
  • Using this model as a basis for both BDD and SMT
    model checking
  • FAC 08

48
Hybrid Automata
  • Verimag
  • Using dense time automata to model behaviors of
    analog circuits
  • Analog assertions and monitors
  • FMCAD 04, FAC 08

49
Reachability Analysis
  • CMU
  • Forward and backward reachability analysis on
    over-approximated partitions
  • DATE 06

50
Bond Graph Abstraction
  • Concordia
  • Abstract the properties of analog circuits into a
    representation based on Bond Graphs
  • Constraint solving to reason about safety and
    reachability properties
  • FAC 08

51
Example 2 Moving up the AMS food chain
  • Phase Locked Loops are critical components of
    most high speed PHYs
  • They are made up of subcomponents
  • Phase detector
  • Charge pump
  • Linear filter
  • Voltage Controlled Oscillator
  • Divider
  • There are many possible failure modes
  • Simulating the locking behavior of a PLL at the
    transistor level in the time domain is very
    expensive

52
PLL locking bugs
53
PLL Locking Bugs (II)?
54
PLL Locking Bugs (IV)?
55
PLL Locking Bugs (V)?
56
A Verification Nightmare
  • Individual components can be wrong
  • Individual components can be fine but assumptions
    between components can be wrong
  • Most of these issues are not visible if we assume
    correct initialization i.e. we start simulation
    from a locked state, as we do for most parametric
    simulation
  • It takes a very (very, very, ) long time to
    simulate, using sufficiently accurate models,
    from any arbitrary initial state to reach lock
  • Bugs like these make it through to production

57
Open Analog Problems (A Challenge)?
  • Avoiding transient simulation
  • Establishing that operating point assumptions are
    valid
  • Establishing that all initial conditions result
    in correct behavior
  • Dealing with non-linearity
  • Good candidates for FM approaches

58
Conclusions and Future Work
  • Analog and digital are different
  • Different mindsets, different tools, different
    problems
  • There are problems in the analog space that are
    really looking for solutions
  • Different points of view yield valuable
    approaches
  • The FV community is just beginning to come to
    grips with this problem gtLots of interesting
    opportunities
  • We can provide realistic examples to interested
    parties
  • Some are small, representative and tractable
  • If any one really wants it, we have a software ?
    digital ? analog ? physics problem (ms ? ns ? ps
    ? fs) in a 20GB SERDES system

59
Some Further Reading
  • General Analog Design
  • Gray Meyer Analysis and Design of Analog
    integrated Circuits, Wiley.
  • B. Razavi Design of Analog CMOS Integrated
    Circuits, McGrawHill
  • Verification issues for Analog/MS
  • Thomas Sheffler, Kathryn Mossawir, Kevin Jones
    PHY Verification - What's Missing?, DVCon 2007
  • More information on Domain Transformation
  • Jaeha Kim, Kevin D. Jones, Mark A. Horowitz
    Variable domain transformation for linear PAC
    analysis of mixed-signal systems. ICCAD 2007
    887-894
  • The State of the Art for Formal Verification of
    Analog Circuits
  • Proceedings of FAC 08
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