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## Chapter 3a Static Timing Analysis

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### Chapter 3a Static Timing Analysis Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe_at_ee.ucla.edu – PowerPoint PPT presentation

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Title: Chapter 3a Static Timing Analysis

1
Chapter 3a Static Timing Analysis
• Prof. Lei He
• Electrical Engineering Department
• University of California, Los Angeles
• URL eda.ee.ucla.edu
• Email lhe_at_ee.ucla.edu

2
Outline
• Motivation
• Modeling
• Algorithm
• Summary

3
Motivation
• Given a gate-level netlist
• Does the netlist meet the timing spec?
• How fast can it be clocked?
• Where is the critical path?
• Can the design be optimized?
• Performance
• Timing analysis
• Quite complicated in the real world
• Well touch some of the basics

4
Dynamic v.s. Static Simulation
• Dynamic timing analysis
• Start time ? end time
• Inputs are fully specified (input patterns)
• SPICE!
• Pro accurate
• Con super slow for large circuits
• Static timing analysis
• Separate timing analysis and function
verification
• Characterize circuit timing independent of inputs
and time periods
• Worst case analysis
• Work at the extremes ? guarantee work always

5
Outline
• Motivation
• Modeling
• Algorithm
• Summary

6
STA Assumptions
• Design is synchronous
• Signal can be arbitrary
• Signal may take any value (0/1)
• Signal can switch at any time within the cycle
• Worst case assumption
• Signal becomes stable at the latest possible time
• Signal becomes unstable at the earliest possible
time

7
STA Close Lookup
• All storage elements are latch or FF
• Cycles cut by clocked storage elements
• STA characterizes timing of combinational parts
between storage elements

8
Single Path Delay Computation
• Path delay sum of 50 propagation delay

9
Device Delay Models
• Unit delay model
• Delay through ANY gate is 1 time unit
• Const gate delay model
• Different gates have different delays

10
Device Delay Models
• Delay is a function of fanout/slew
• Table based
• Input pins are different

11
Interconnect Delay Model
• Interconnect delay becomes a dominant portion of
total delay
• Lumped RC model
• Distributed RC model
• As frequency increases, RLC model may be
necessary

12
Interconnect Delay Model
• Delay for RC trees
• Rubinstein-Penfield Theorem
• For our purpose, we assume point-to-point wiring
delays are pre-characterized as cell delays
• Different interconnect have different delays

13
Putting things together
• Interconnect delay in red
• Gate delay in blue
• Arrival time in green

14
Combinational Block Modeling Delay Graph
• Labeled directed acyclic Graph (DAG)
• Vertices gates, PI, PO
• Edges Interconnect
• Labels delays

15
Outline
• Motivation
• Modeling
• Algorithm
• Summary

16
Path-based STA
• Path enumeration
• List all paths, output path delays
• Algorithms
• It works, but whats the problem?

17
Path Enumeration
• Problem is the number of paths
• Can be exponential growth
• Total paths 2n

18
Block Based STA
• Arrival times (AT) at a node
• Time when signal arrives at the node
• Latest time signal can become stable
• Determined by longest path from source

19
Block Based STA
• Required arrival time (RAT) at a node
• Time before which signal must arrive to avoid
timing violation
• Latest time signal is allowed to become stable
• Determined by longest path to sink

20
AT Computation Kirkpatrick 1966
• AT at node n
• Longest path delay from source to node n
• Longest path Forward-prop(source)
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed
• Linear algorithm operates on DAG

21
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

22
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

23
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

24
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

25
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

26
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

27
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

28
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

29
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

30
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

31
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

32
AT Computation illustrated
• Forward-prop(W)
• For each vertex v in W
• For each edge ltv,wgt from v
• Final-delay(w)max(Final-delay(w),
delay(v)delay(w)delay(ltv,wgt))
• If all incoming edges of w have been traversed

33
• RAT required arrival time
• Backtrack from sinks

34
Timing Slack
• Each node AT RAT
• Timing slack RAT-AT
• Reflects criticality of a node
• Negative timing violation, node is no critical
path
• Positive extra timing budget
• Optimize for power/area/robustness
• Slack distribution is KEY for timing
optimization!!
• An example assuming RAT(f)5.80

35
Logical v.s. Topological
• So far we have ignored the logic details for
each vertices
• Topological timing analysis
• We dont care the logic functionality
• Major assumption for STA
• Major flaw due to this false path
• In contrast, for logical timing analysis
• We care the logic functionality

36
False Path in STA
• A major (critical) assumption hidden behind STA!
• All paths are sensitizable
• There always exists a set of inputs that will
cause the logic propagating along any chosen path
• But this is NOT true in general

37
False Path Example Carry Bypass Adder
• Our previous algorithm will identify the red
path as the longest path!
• Is this path sensitizable?

38
False Path Example Carry Bypass Adder
• To sensitize red path we need
• ai XOR bi ai1 XOR bi1
• But red path is false
• When above condition is true, MUX selects 1
input, i.e. directly from ci-1
• Instead shorter green paths are sensitized
• Hence, red path is not the critical path of the
circuit!

39
False Path Aware STA
• False path is universal for STA
• Causes a lot of pain for STA
• Determining sensitization path is very hard
• As hard as Boolean Satisfiability (SAT) problem,
which is proven NP-hard
• Fortunately, there exist a lot of effective
heuristics
• Beyond the scope

40
Summary
• STA is a very powerful tool for chip sign-off
• Delay modeling (device interconnect)
• DAG for timing analysis
• AT/RAT/Slack computation algorithms
• False path in STA

41