SEU-Hardened Storage Devices in a 0.15

1
SEU-Hardened Storage Devices in a 0.15 µm
Antifuse FPGA RTAX-S

• J. J. Wang1, B. Cronquist1, J. McCollum1, R.
  Gorgis1, R. Katz2, and I. Kleyner3
• 1 Actel Corporation2 NASA Office of Logic
  Design3 Orbital Science, Greenbelt, MD20771

2
Abstract

• The storage devices in the RTAX-S family are
  SEU-hardened. The flip-flop is hardened by
  hard-wired triple module redundancy, and the RAM
  is hardened by software error-correcting code
  (ECC), which is a shortened Hamming code.
• These hardened storage devices are tested by
  heavy ion beam, and their SEU cross sections are
  extracted from test data for rate predictions in
  a typical environment. Final results show that
  both devices are hardened effectively, and the
  measured upset errors are due to SET and noise.

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Triple Module Redundant Flip-Flop(K-Latch)
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TMR Flip-Flop Heavy Ion Beam Test

• Device under test
• RTAX2000-S
• Four pre-production devices
• Logic design
• Two 100-bit shift registers, SH1 and SH2, for SEU
  measurement
• Two user-level TMR shift registers for noise
  monitoring
• Checkerboard pattern running at 2 MHz during
  irradiation
• -10 VCC for SEU measurement, 10 VCC for SEL
  and SEDR
• Heavy ion beam
• BNL Tandem Van de Graaff
• Cl-35, Ni-58, Br-81, I-127
• Effective LET37.5 to 104 MeVcm2/mg

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Hard-wired TMR Flip-Flop Cross Section per bit
Weibull Fit
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TMR Flip-Flop SEU Rate Prediction

• Use Space Radiation 4.5 simulator
• Weibull parameters LET010MeVcm2/mg,
  width35MeVcm2/mg, shape2, saturation
  cross-section9x10-10cm2
• Active volume depth0.15µm, funnel depth0.3µm
• Environment GEO solar minimum
• Shielding 100mil Aluminum
• Upsets Rate
• 1.96x10-11 upsets/bitday
• Based on RTSX-S experiences, the measured upsets
  are probably due to SET and testing noise

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EDAC-RAM in RTAX-S

• ECC
• Shortened Hamming code to detect 2 errors and
  correct 1 error
• S. Lin and D. J. Cosello, Jr., Error Control
  Coding Fundamentals and Applications, Prentice
  Hall, New Jersey, 1983
• http//www.actel.com/documents/EDAC_AN.pdf Using
  EDAC RAM for RadTolerant RTAX-S FPGAs and
  Axcelerator FPGAs
• Scrubbing
• Reduce SEU rate for long-term storage
• User selects the scrubbing rate
• Word width

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ACTgen Creates EDAC-RAM
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EDAC-RAM Implementation
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EDAC-RAM Heavy Ion Beam Test

• Test logic designed by ACTgen macro
• Beam test uses very high fluxes (1x104-1x105
  Ions/cm2/sec)
• Have to turn on scrubbing during irradiation
• Test ports not used
• ECC and scrubbing are tested simultaneously
  because scrubbing alone cannot reduce SEU

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EDAC-RAM BNL Test Data
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EDAC-RAM SEU Cross-Section per 8-bit Word
Weibull Fit
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RAM SEU Cross-Section per Single Bit
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EDAC-RAM SEU Rate Prediction

• Use Space Radiation 4.5 simulator
• Weibull parameters LET030MeVcm2/mg,
  width10MeVcm2/mg, shape1.5, saturation
  cross-section3.91x10-9cm2
• Active volume depth0.15µm, funnel depth0.3µm
• Environment GEO solar minimum
• Shielding 100mil Aluminum
• Upsets Rate Boundary
• 8-bit word is lt 2.55x10-11 upsets/wordday
• 16-bit word is lt 1.57x10-10 upsets/wordday
• 32-bit word is lt 4.18x10-10 upsets/wordday

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EDAC-RAM TAMU Test Data
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Scrubbing Rate Dependence

• Predicted upsets derived from single-bit-upset
  cross section and probability theory
• Prediction and Experiment match at high upsets
  but not at low upsets
• Low upsets in Experiment may be due to SET and
  noise

Clock Freq Refresh Period Exper Upset Predicted Upset
2 MHz 512 µs 1 0.00265
100 kHz 10 ms 2 0.0529
10 kHz 0.1 s 5 0.529
1 kHz 1 s 8 5.29
100 Hz 10 s 54 52.9
No Scrubbing 100 s 150 166
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Conclusions

• Hard-wired TMR flip-flop is radiation hard.
• The measured upset errors in hardened flip-flops
  are probably due to SET and noise.
• EDAC-RAM is radiation hard, which means the ECC
  scheme and scrubbing are performing as expected.
• Low level upsets measured in EDAC-RAM are
  probably due to SET and noise.