Link A/D converters and Microcontrollers using Long Transmission Lines PowerPoint PPT Presentation

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Title: Link A/D converters and Microcontrollers using Long Transmission Lines


1
Link A/D converters and Microcontrollers using
Long Transmission Lines
  • John WUPrecision Analog - Data Converter
    Applications Engineerwu_john_at_ti.com

2
Transmission Line Effect Considerations
  • Definition of the Highest Frequency Signal
  • Transmission Line Model
  • Reflection Concept
  • Termination Topology
  • Crosstalk Analysis

3
Application Example
4
Transmitted Data and Clock
5
Reflection on MSP430
6
With Termination on MSP430
7
Reflection on ADS8326 EVM
8
With Termination on ADS8326
?
9
Definition of the highest frequency signal
  • What is the highest frequency signal
  • in a 2.25MHz sample clock rate
  • ADC ?

10
Definition of the highest frequency signal
The highest frequency signal is determined by the
signal rise or fall time
11
Rise Time vs. Bandwidth
  • The rise time and bandwidth are related by
  • For example
  • clock rate 2.25 MHz,
  • trise CLK 10 ns
  • trise Data 2 ns
  • The highest frequency signal or bandwidth is

175MHz
12
Rise Time Measurement
  • The displayed Tr 2ns (10-90) on an
    oscilloscope
  • 3-dB bandwidth of a probe is 500MHz (Tr 0.7ns)
  • 3-dB bandwidth of an oscilloscope input is 350MHz
    (Tr1ns)
  • What is the measured input signal Tr ?

13
Rise Time Degradation
  • Tdisplayed2 Tprobe2 Tscope2 Tsignal2
  • Tsignal2 Tdisplayed2 -Tprobe2 -Tscope2
  • Tsignal SQRT(22 - 0.72 - 12 )1.6ns!
  • 1.6ns) 220MHz

14
Critical Microstrip Length
  • What is the critical length of
  • a microstrip that must be considered as
    transmission line?

15
Rise Time vs. Propagation Delay
16
Propagation Delay vs. Dielectric Constant
17
Critical Microstrip Length
  • Tr x 15 1.6ns x 15 226 ps
  • 1.5 inch

18
Transmission Line Model
19
Characteristic Impedance of Twisted Pair Cable
Microstrip

20
Reflection Factor

Zo
Z L
If Z L gtgt Zo ? 1 If Z L ltlt Zo ?
-1
21
S Parameters for Reflection
22
Reflection Analysis
23
Reflection Calculation
24
Calculated vs. Measured Reflection
  • Tr/7

25
Critical Length of a Transmission Line
  • What is the critical length of
  • a transmission line that must be terminated?

26
Rise Time vs. Propagation Delay
27
Trace Cable Terminations
  • Source Termination

Receiver
Driver
Zo 50 W
Rt
Rs
Rt Rs Zo
28
Trace Cable Terminations
  • AC termination

AC Termination
29
Place of Terminations
  • Daisy Chain Routing with Stubs

Clock Source
Clock Bus
Termination Resistor
Stub
Device 1
Device 2
Device Pin BGA Ball
30
Short stubs create signal integrity problems
  • Stub Length0.5
  • Stub Length0.25
  • Reference
  • Altera
  • application note 224

31
Daisy Chain Routing without Stubs
Device Pin BGA Ball
Clock Source
Clock Bus
Device 1
Device 2
Termination Resistor
32
Star Routing
Clock Bus
Device 1
Termination Resistor
Device 2
Clock Source
Device 3
Device Pin BGA Ball
33
Parallel Fly-By Termination
Vcc
R1
Zo 50 W
Receiver Device (BGA Package)
R2
34
Differential Pair (LVDS) Fly-By Termination
Receiver Device (BGA Package)
Zo50 W
100 W
Zo50 W
35
Crosstalk Analysis
  • Cross Talk occurs on PCB and twisted wire cable

36
Magnetic Electric Fields of Parallel
Transmission Line

Victim Trace
Aggressor Trace
Aggressor Trace
Victim Trace
Magnetic Field
Electric Field
Ground Plane
Ground Plane
37
Cross Talk Analysis
38
Cross Talk Analysis
39
FEXT Measurement
Inductive or Capacitive Coupling ?
40
Reduced FEXT Measurement
41
NEXT Measurement
42
Reduced NEXT Measurement
43
Separated Data Wire
44
Cross Talk Reduced by Termination
X-talk
45
Final Termination Solution
46
Conclusions
  • The highest frequency signal is determined by
    switching time
  • Transmission line model must be used when
    propagation delay time is greater than 15 of Tr
  • Termination technique dramatically reduces
    reflection and crosstalk
  • QA

47
Acknowledgement
  • Thanks Phil Lizzi for providing the real life
    transmission line application example
  • Reference
  • Managing Signal Quality Mentor Graphics/Xilinx,
    2005 http//www.xilinx.com/publications/xcellonlin
    e/xcell_53/xc_pdf/xc_mentor53.pdf
  • High-Speed Board Layout Guideline Altera
    application note 224, Sept. 2003
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