THE PROGRAMMABLE LOGIC CONTROLLER

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THE PROGRAMMABLE LOGIC CONTROLLER
Slovak University of Technology Faculty of
Material Science and Technology in Trnava

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Programmable Logic Controller (PLC)

• PLCs have been gaining popularity on the factory
  floor is because of the advantages they offer
• Cost effective for controlling complex systems.
• Flexible and can be reapplied to control other
  systems quickly and easily.
• Computational abilities allow more sophisticated
  control.
• Trouble shooting aids make programming easier and
  reduce downtime.
• Reliable components make these likely to operate
  for years before failure.

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A PLC illustrated with relays
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Origins of Ladder Diagram

• The Ladder Diagram (LD) programming language
  originated from the graphical representation used
  to design an electrical control system
• Control decisions were made using relays
• After a while Relays were replaced by logic
  circuits
• Logic gates used to make control decisions
• Finally CPUs were added to take over the function
  of the logic circuits
• I/O Devices wired to buffer transistors
• Control decisions accomplished through
  programming
• Relay Logic representation (or LD) was developed
  to make program creation and maintenance easier
• Computer based graphical representation of wiring
  diagrams that was easy to understand
• Reduced training and support cost

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Origins of Ladder Diagram
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What is a Rung?

• A rung of ladder diagram code can contain both
  input and output instructions
• Input instructions perform a comparison or test
  and set the rung state based on the outcome
• Normally left justified on the rung
• Output instructions examine the rung state and
  execute some operation or function
• In some cases output instructions can set the
  rung state
• Normally right justified on the rung

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Series Vs Parallel Operations

• Ladder Diagram input instructions perform logical
  AND and OR operations in and easy to understand
  format
• If all Input Instructions in series must all be
  true for outputs to execute (AND)
• If any input instruction in parallel is true, the
  outputs will execute (OR)
• Paralleling outputs allows multiple operations to
  occur based on the same input criteria

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Ladder Logic Execution

• Rungs of Ladder diagram are solved from Left to
  right and top to bottom
• Branches within rungs are solved top left to
  bottom right

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Non Retentive Coils

• The referenced bit is reset when processor power
  is cycled
• Coil -( )-
• Sets a bit when the rung is true(1) and resets
  the bit when the rung is false (0)
• PLC5 calls this an OTE Output Enable
• Negative coil -( / )-
• Sets a bit when the rung is false(0) and resets
  the bit when the rung is True(1)
• Not commonly supported because of potential for
  confusion
• Set (Latch) coil -(S)-
• Sets a bit (1) when the rung is true and does
  nothing when the rung is false
• Reset (Unlatch) Coil -(R)-
• Resets a bit (0) when the rung is true and does
  nothing when the rung is false

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Contacts

• Normally Open Contact - -
• Enables the rung to the right of the instruction
  if the rung to the left is enabled and
  underlining bit is set (1)
• Normally Closed Contact -/-
• Enables the rung to the right of the instruction
  if the rung to the left is enabled and
  underlining bit is reset (0)
• Positive transition contact -P-
• Enables the right side of the rung for one scan
  when the rung on left side of the instruction is
  true
• Allen Bradley PLC5 uses -ONS-
• Negative transition contact -N-
• Enables the right side of the rung for one scan
  when the rung on left side of the instruction is
  false

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Retentive Vs Non-retentive Operation

• Definitions
• Retentive values or instructions maintain their
  last state during a power cycle
• Non-retentive values or instructions are reset to
  some default state (usually 0) after a power
  cycle
• IEC1131 permits values to be defined as retentive
• A contradiction to this is ladder diagram where 3
  instructions are classified as retentive
• In most PLCs only timer and coil instructions
  operate as non-retentive

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Retentive Coils

• The referenced bit is unchanged when processor
  power is cycled
• Retentive coil -(M)-
• Sets a bit when the rung is true(1) and resets
  the bit when the rung is false (0)
• Set Retentive (Latch) coil -(SM)-
• Sets a bit (1) when the rung is true and does
  nothing when the rung is false
• PLC5 uses OTL Output Latch
• Reset Retentive (Unlatch) Coil -(RM)-
• Resets a bit (0) when the rung is true and does
  nothing when the rung is false
• PLC5 uses OUT Output Unlatch

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Transition Sensing Coils

• Positive transition-sensing coil -(P)-
• Sets the bit bit (1) when rung to the left of the
  instruction transitions from off(0) to on(1)
• The bit is left in this state
• PLC5 use OSR (One Shot Rising)
• Negative transition-sensing coil -(N)-
• Resets the bit (0) when rung to the left of the
  instruction transitions from on(1) to off(0)
• The bit is left in this state
• PLC5 uses OSF (One Shot Falling)

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IEC Comparison Instructions in Ladder

• If the rung input (EN) is enabled, the
  instruction performs the operation and sets the
  rung output (ENO) based on the comparison
• Example when EN is true, EQ () function
  compares In1 and to In2 and sets ENO
• Comprehensive instruction set
• EQ(), GT (gt), GE (gt), LT (lt), LE (lt), NE (ltgt)

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Timers in Ladder Diagram

• There three timer instructions in IEC1131
• TP - Pulse timer
• TON - Timer On Delay
• TOF - Timer Off Delay
• Time values
• Time base is 1msec (1/1000 of a sec)
• Values entered using duration literal format
• Two possible visualizations Depending on use of
  EN/ENO
• 1st method requires extra programming if timer
  done status needs to be referenced on other rungs
• 2nd method sets a bit with Q which can be
  referenced by other logic, ENOEN

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Timer Operation

• IN Rung input condition
• Q Comparison output results
• Varies with timer types
• PT Preset Time
• ET Elapse Time

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Counters in Ladder Diagram

• There three counter instructions in IEC1131
• CTU - Count Up Counter
• CTD - Count Down Counter
• CTUD - Count Up/Down Counter
• All three count rung transitions
• Two possible visualizations Depending on use of
  EN/ENO
• 1st method requires extra programming if timer
  done status needs to be referenced on other rungs
• 2nd method sets a bit with Q which can be
  referenced by other logic, ENOEN

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Counter Operation

• Parameters
• CU/CD Count up/Down
• Q/QU/QD Comparison Output
• R Reset to Zero
• LD Load CV with PV
• PV Preset Value
• CV Count Value

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Execution Control Elements

• Jump / Label Instructions
• Jump to a label skips a block of code without it
  being scanned
• LBL - Named target for a jump operation
• JMP - Performs a jump when the rung conditions
  are true

• CALL / RETURN Instructions
• Used to encapsulate logic and call it as a
  subroutine
• Causes execution to change between functions or
  subroutines
• CAL - Passes control to another named function
• PLC5 uses JSR
• RET - Exits a function and returns control back
  to the calling routine

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Different Instruction Presentations

• The look and feel of IEC 1131-3 is somewhat
  different from the 1Million PLCs that Allen
  Bradley has running in factories throughout the
  world
• IEC places the input parameters on the outside of
  the instruction block vs the PLC5 where they are
  presented inside of the block

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Extending the IEC1131-3 Instruction Set

• IEC1131-3 Provides a very basic set of
  instructions to do simple operations (81 Ladder
  Diagram Instructions)
• Data Type Conversion - Trunc, Int_to_Sint,
  Dint_to_Real, Bcd_To_Int
• Boolean Operations - Bit Test, Bit Set, One Shot,
  Semaphores
• Timers / Counters - Ton, Tp, Ctu, Ctd, Ctud
• Simple Math - Add, Sub, Mul, Div, Mod, Move, Expt
• Misc. Math - Abs, Sqrt, Ln, Log, Exp, Sin, Cos,
  Tan, Asin, Acos, Atan
• Bit Shift - Shl, Shr, Ror, Rol
• Logic - And, Or, Xor, Not
• Selection - Sel, Max, Min, Limit, Mux
• Compare - GT, GE, EQ, LE, LT, NE
• String - Len, Left, Right, Mid, Concat, Insert,
  Delete, Replace, Find
• Control - JMP, LBL, JSR, RET
• All complex operations are left to the user or
  vendor to define
• File Operations, PID, Diagnostic, For/Nxt Loop,
  Search, Sort are not in IEC1131-3
• Extensions to the instruction set are permitted
  so that vendors can add instructions that their
  customers need
• All vendors have defined their own set of
  extensions
• Rockwell Automation controllers have
  significantly more capabilitywith over 130
  Ladder Instructions

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PLC HARDWARE

• The most essential components PLC are
• Power Supply - 24Vdc, 120Vac, 220Vac.
• CPU (Central Processing Unit) - This is a
  computer where ladder logic is stored and
  processed.
• I/O (Input/Output) - A number of input/output
  terminals must be provided so that the PLC can
  monitor the process and initiate actions.
• Indicator lights - These indicate the status of
  the PLC including power on, program running, and
  a fault. These are essential when diagnosing
  problems.

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PLC HARDWARE

• Typical configurations are listed below from
  largest to smallest
• Rack - A rack is often large (up to 18 by 30 by
  10) and can hold multiple cards. When necessary,
  multiple racks can be connected together. These
  tend to be the highest cost, but also the most
  flexible and easy to maintain.
• Mini - These are similar in function to PLC
  racks, but about half the size.
• Shoebox - A compact, all-in-one unit (about the
  size of a shoebox) that has limited expansion
  capabilities. Lower cost, and compactness make
  these ideal for small applications.
• Micro - These units can be as small as a deck of
  cards. They tend to have fixed quantities of I/O
  and limited abilities, but costs will be the
  lowest.
• Software - A software based PLC requires a
  computer with an interface card, but
• allows the PLC to be connected to sensors and
  other PLCs across a network.

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INPUTS FOR A PLC

• Inputs for a PLC come in a few basic varieties,
  the simplest are AC and DC inputs. Sourcing and
  sinking inputs are also popular
• Sinking - When active the output allows current
  to flow to a common ground. This is best selected
  when different voltages are supplied.
• Sourcing - When active, current flows from a
  supply, through the output device and to ground.
  This method is best used when all devices use a
  single supply voltage.

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INPUTS FOR A PLC

• In smaller PLCs the inputs are normally built in
  and are specified when purchasing the PLC.
• For larger PLCs the inputs are purchased as
  modules, or cards, with 8 or 16 inputs of the
  same type on each card.
• Inputs are normally high impedance. This means
  that they will use very little current.

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INPUTS FOR A PLC

• There are many trade-offs when deciding which
  type of input cards to use.
• DC voltages are usually lower, and therefore
  safer (i.e., 12-24V).
• DC inputs are very fast, AC inputs require a
  longer on-time. For example, a 60Hz wave may
  require up to 1/60sec for reasonable recognition.
• DC voltages can be connected to larger variety of
  electrical systems.
• AC signals are more immune to noise than DC, so
  they are suited to long distances, and noisy
  (magnetic) environments.
• AC power is easier and less expensive to supply
  to equipment.
• AC signals are very common in many existing
  automation devices.

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PLC Input Circuits
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Output Modules

• External power supplies are connected to the
  output card and the card will switch the power on
  or off for each output. Typical output voltages
  are listed below, and roughly ordered by
  popularity.
• 120 Vac
• 24 Vdc
• 12-48 Vac
• 12-48 Vdc
• 5Vdc (TTL)
• 230 Vac

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PLC Output Circuits
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24Vdc Output Card (Sinking)
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24Vdc Output Card With a Voltage Input (Sourcing)
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Relay Output Card
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MEMORY TYPES
RAM (Random Access Memory) - this memory is fast,
but it will lose its contents when power is
lost, this is known as volatile memory. Every
PLC uses this memory for the central CPU when
running the PLC. ROM (Read Only Memory) - this
memory is permanent and cannot be erased. It is
often used for storing the operating system for
the PLC. EPROM (Erasable Programmable Read Only
Memory) - this is memory that can be programmed
to behave like ROM, but it can be erased with
ultraviolet light and reprogrammed. EEPROM
(Electronically Erasable Programmable Read Only
Memory) - This memory can store programs like
ROM. It can be programmed and erased using a
voltage, so it is becoming more popular than
EPROMs.
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MEMORY ADDRESSES
The memory in a PLC is organized by data type as
shown in Figure
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PROGRAM FILES

• In a PLC-5 (Allen-Bradley PLCs ) the first three
  program files, from 0 to 2, are defined by
  default
• File 0 contains system information and should not
  be changed
• File 1 is reserved for SFCs.
• File 2 is available for user programs and the PLC
  will run the program in file 2 by default.
• Other program files can be added from file 3 to
  999. Typical reasons for creating other programs
  are for subroutines.

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DATA FILES

• Data files are used for storing different
  information types, as shown in Figure

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Allen-Bradley Data Types
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Bit Level Addressing
Memory bits are normally indicated with a forward
slash followed by a bit number /n.
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Integer Word Addressing

• Entire words can be addressed as shown in Figure.
• These values will normally be assumed to be 2s
  compliment, but some functions may assume
  otherwise

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Literal Data Values

• Data values do not always need to be stored in
  memory, they can be define literally.
• Figure shows an example of two different data
  values

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File Addressing

• Sometimes we will want to refer to an array of
  values, as shown in Figure.
• This data type is indicated by beginning the
  number with a pound or hash sign .

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Indirect Addressing

• Indirect addressing is a method for allowing a
  variable in a data address, as shown in Figure.
• The indirect (variable) part of the address is
  shown between brackets and .

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Expression Data Values

• Expressions allow addresses and functions to be
  typed in and interpreted when the program is run.
• The example in Figure will get a floating point
  number from file 8, location 3, perform a sine
  transformation, and then add 1.3.

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An Example of Ladder Logic Functions

• The basic operation is such that while input A is
  true the functions will be performed.

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User Bit Memory

• The bit memory can be accessed with individual
  bits or with integer words.

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Status Bits and Words (Allen-Bradley Micrologic )
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BOOLEAN LOGIC DESIGN

• Boolean Operations

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The Basic Axioms of Boolean Algebra
Duality interchange AND and OR operators, as well
as all Universal, and Null sets. The resulting
equation is equivalent to the original.
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Reverse Engineering of a Digital Circuit
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KARNAUGH MAPS
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KARNAUGH MAPS
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KARNAUGH MAPS
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Sequential Design Techniques
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PROCESS SEQUENCE BITS

• The steps for this design method are
• Understand the process.
• Write the steps of operation in sequence and give
  each step a number.
• For each step assign a bit.
• Write the ladder logic to turn the bits on/off as
  the process moves through its states.
• Write the ladder logic to perform machine
  functions for each step.
• If the process is repetitive, have the last step
  go back to the first.

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Process Sequence Bits Without Latches
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TIMING DIAGRAMS

• Timing diagrams can be valuable when designing
  ladder logic for processes that are only
  dependant on time. The basic method is
• 1. Understand the process.
• 2. Identify the outputs that are time dependant.
• 3. Draw a timing diagram for the outputs.
• 4. Assign a timer for each time when an output
  turns on or off.
• 5. Write the ladder logic to examine the timer
  values and turn outputs on or off.

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TIMING DIAGRAMS
Description A handicap door opener has a button
that will open two doors. When the button is
pushed (momentarily) the first door will start to
open immediately, the second door will start to
open 2 seconds later. The first door power will
stay open for a total of10 seconds, and the
second door power will stay on for 14 seconds.
Use a timing diagram to design the ladder logic.
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FLOWCHART BASED DESIGN

• A flowchart is ideal for a process that has
  sequential process steps.
• The symbols used for flowcharts are

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FLOWCHART BASED DESIGN

• The general method for constructing flowcharts
  is
• 1. Understand the process.
• 2. Determine the major actions, these are drawn
  as blocks.
• 3. Determine the sequences of operations, these
  are drawn with arrows.
• 4. When the sequence may change use decision
  blocks for branching.

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A Flowchart for a Tank Filler
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BLOCK LOGIC

• STEP 1 Add labels to each block in the flowchart

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BLOCK LOGIC
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BLOCK LOGIC
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BLOCK LOGIC
The ladder logic for operation F2 is simple, and
when the start button is pushed, it will turn off
F2 and turn on F3. The ladder logic for
operation F3 opens the inlet valve and moves to
operation F4
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BLOCK LOGIC
The ladder logic for operation F4 turns off F4,
and if the tank is full it turns on F6, otherwise
F5 is turned on. The ladder logic for operation
F5 is very similar. The ladder logic for
operation F6 turns the outlet valve on and turns
off the inlet valve. It then ends operation F6
and returns to operation F2
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STATE BASED DESIGN

• A State based system can be described with system
  states, and the transitions between those states.

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STATE BASED DESIGN

• The most essential part of creating state
  diagrams is identifying states. Some key
  questions to ask are

1. Consider the system What does the system
do normally? Does the system behavior
change? Can something change how the system
behaves? Is there a sequence to actions?
2. List modes of operation where the system is
doing one identifiable activity that will
start and stop. Keep in mind that some
activities may just be to wait.
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STATE BASED DESIGN

• Consider the design of a coffee vending machine.
• The first step requires the identification of
  vending machine states as shown in

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STATE BASED DESIGN

• STATES
• idle - the machine has no coins and is doing
  nothing,
• inserting coins - coins have been entered and
  the total is displayed,
• user choose - enough money has been entered and
  the user is making coffee selection,
• make coffee - the selected type is being made,
• service needed - the machine is out of coffee,
  cups, or another error has occurred.

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STATE BASED DESIGN

• The states are then drawn in a state diagram as
  shown in

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Basic PLC Function Categories

• Lists
• - shift registers/stacks
• - sequencers
• Program Control
• - branching/looping
• - immediate inputs/outputs
• - fault/interrupt detection
• Input and Output
• - PID
• - communications
• - high speed counters
• - ASCII string functions

• Combinatorial Logic
• - relay contacts and coils
• Events
• - timer instructions
• - counter instructions
• Data Handling
• - moves
• - mathematics
• - conversions
• Numerical Logic
• - boolean operations
• - comparisons

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Move Functions

• MOV(value, destination) - moves a value to a
  memory location
• MVM(value, mask, destination) - moves a value to
  a memory location, but with a mask to select
  specific bits.

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Mathematical Functions
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Advanced Mathematical Functions
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Conversions

• The example function will retrieve a BCD number
  from the D type (BCD) memory and convert it to a
  floating point number that will be stored in
  F82.

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Statistic Functions

• When A becomes true the average (AVE) conversion
  will start at memory location F80 and average a
  total of 4 values. The control word R61 is used
  to keep track of the progress of the operation,
  and to determine when the operation is complete.

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Block Operation Functions

• A basic block function is shown in Figure 10.13.
  This COP (copy) function will copy an array of 10
  values starting at N750 to N740.

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Comparison Functions

• Comparison functions are shown in Figure.
• The example shows an EQU (equal) function that
  compares two floating point numbers. If the
  numbers are equal, the output bit B35/1 is true,
  otherwise it is false.

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Boolean Functions

• The function shown will obtain data words from
  bit memory, perform and operation, and store the
  results in a new location in bit memory. These
  functions are all oriented to word level
  operations. The ability to perform Boolean
  operations allows logical operations on more than
  a single bit.

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Boolean Function Example
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Shift Register Functions
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Shift Register Variations
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Buffers and Stack Types
Stacks store integer words in a two ended buffer.
There are two basic types of stacks
first-on-first-out (FIFO) and last-in-first-out
(LIFO).
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The Basic Sequencer Instruction

• A PLC sequencer uses a list of words in memory.
  It recalls the words one at a time and moves the
  words to another memory location or to outputs.
  When the end of the list is reached the sequencer
  will return to the first word and the process
  begins again.

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A JMP Instruction

• These functions allow parts of ladder logic
  programs to be included or excluded from each
  program scan

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A Fault Recovery Program
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A Timed Interrupt Program

• A timed interrupt will run a program at regular
  intervals. To set a timed interrupt the program
  in file number should be put in S231. The
  program will be run every S230times 1
  milliseconds.

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Immediate I/O Instructions

• Input, Program and Output Scan

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Immediate Inputs and Outputs
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Design techniques

• This state diagram shows three states with four
  transitions.
• There is a potential conflict between transitions
  A and C.

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The Main Program for the State Diagram
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Subroutines for the States
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A Modified State Diagram to Prevent Racing

• Figure shows a technique that blocks race
  conditions by blocking a transition out of a
  state until the transition into a state is
  finished. The solution may not always be
  appropriate.

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Design cases. If-Then.

• Problem Convert the following C/Java program to
  ladder logic.

void main() int A for(A 1 A lt 10 A) if
(A gt 5) then A add(A) int add(int x) x
x 1 return x
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INSTRUCTION LIST PROGRAMMING

• A simple example is shown in Figure using the
  definitions found in the IEC standard

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A Structured Text Example Program

• This program counts from 0 to 10 with a loop.

PROGRAM main VAR i INT END_VAR i
0 REPEAT i i 1 UNTIL i gt
10 END_REPEAT END_PROGRAM
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FUNCTION BLOCK PROGRAMMING

• A Simple Comparison Program.
• In this program the inputs N70 and N71 are used
  to calculate a value sin(N70) ln(N71). The
  result of this calculation is compared to N72.
  If the calculated value is less than N72 then
  the output O000/01 is turned on, otherwise it is
  turned off.

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Creating function blocks

• Figure shows a divide function block created
  using ST

99
The IEC 61499 Standard

• A standardization project of IEC Technical
  Committee 65 (TC65) to standardize the use of
  function blocks in distributed industrial-process
  measurement and control systems (IPMCSs).
• Work item approved 1991 assigned to Working
  Group 6 (WG6) 1993
• Experts from USA, Germany, Japan, UK, Sweden,
  France, Italy
• Also responsible for IEC 61131-3 (Programmable
  Controller Languages) and 61131-8 (Programmable
  Controller Language Guidelines)

100
Function Blocks The Architectural Dialectic
101
Architectural Co-Evolution

• IEC 61499
• Parent organization IEC
• Working group TC65/WG6
• Goal Standard model (function blocks) for
  control encapsulation distribution
• Started 10/90
• Active development 3/92
• Trial period 2001-03
• Completion 2005

• Holonic Manufacturing Systems (HMS)
• Parent organization IMS
• Working group HMS Consortium
• Goal Intelligent manufacturing through holonic
  (autonomous, cooperative) modules
• Feasibility study 3/93-6/94
• First phase 2/96 - 6/00
• Second phase 6/00-6/03

102
Intelligent Systems Requirements ofThe IP
Value-Add Chain
103
Architectural Requirements

• Component-Based
• Support encapsulation/protection of Intellectual
  Property (IP)
• IP Portable across Software Tools and Runtime
  Platforms
• Distributed
• Map IP modules into distributed devices
• Integrate IP Modules into distributed
  applications
• Functionally Complete
• Control/Automation/Diagnostics components
• Machine/Process Interface components
• Communication Interface components
• Human/Machine Interface (HMI) components
• Software Agent ("Holonic") components
• Extendable
• Encapsulate new types of IP
• Create new IP through Functional Composition of
  existing IP modules
• OPEN!
• Multiply the value of IP through widest possible
  deployment
• Benefits available to all market players

104
What is an Open Architecture?

• An architecture whose functional units are
  capable of exhibiting portability,
  interoperability and configurability
• portability Software tools can accept and
  correctly interpret library elements produced by
  other software tools.
• interoperability Devices can operate together to
  perform the functions specified by one or more
  distributed applications.
• configurability Devices and their software
  components can be configured (selected, assigned
  locations, interconnected and parameterized) by
  multiple software tools.
• architecture The structure and relationship
  among functional units in a system.
• functional unit An entity of hardware or
  software, or both, capable of accomplishing a
  specified purpose.

105
Requirements for an Open Distributed Architecture
106
IEC 61131-3 Function BlocksComponent-Based
Encapsulation and Reuse
107
IEC 61499 Basic Function Block TypesEncapsulatio
n and Reuse
108
The Execution Control Chart (ECC)An
Event-Driven State Machine
109
Functional Composition and ReuseIEC 61499
Composite Function Block Types
110
IEC 61499 Service Interface Function Blocks

• Access to Resource functionality, e.g., I/O, HMI,
  comms
• Modeled as sequences of service primitives per
  ISO TR 8509

111
IEC 61499 Communication Service
InterfacesPublish/Subscribe Model
112
IEC 61499 Communication Service
InterfacesClient/Server Model
113
IEC 61499 Distributed System Architecture
114
IEC 61499 Device Architecture
115
IEC 61499 Resource Architecture

• Resource schedules executes FB algorithms
• Resource maps Communications Process I/O
  Functions to Service Interface Function Blocks

116
Standard Event Processing Function Blocks

• E_SPLIT/E_MERGE/E_REND - Event split, merge,
  rendezvous
• E_PERMIT - Permissive event propagation
• E_SELECT - 1 of 2 (boolean) event selection
• E_SWITCH - 1 of 2 (boolean) event demultiplexing
• E_DELAY - Event delay (timer)
• E_CYCLE - Periodic event generation
• E_RESTART - Generation of COLD/WARM restart, STOP
  events
• E_TRAIN/E_TABLE/E_N_TABLE - Finite trains of
  events
• E_SR/E_RS/E_D_FF - Event-driven bistables
• E_R_TRIG/E_F_TRIG - Event-driven rising/falling
  edge detection
• E_SR/E_RS/E_D_FF - Event-driven bistables
• E_CTU - Event-driven up-counter
• See IEC 61499-1, Annex A

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Conversion of IEC 61311-3 Function Blocks to 61499
118
IEC 61499 Device Management Architecture

• Separation of Concerns
• Software Tools vs. Runtime Device
• Communication Services vs. Management Services

119
Dynamic Configuration in IEC 61499 The Device
Management Service Interface
120
The IEC 61499 System Management Model
121
IEC 61499 Software Tool Models
122
IEC 61499-2 Software Tool Requirements

• Exchange of library elements
• Information to be provided by the supplier of
  library elements
• Display of declarations
• Modification of declarations
• Validation of declarations
• Implementation of declarations
• System operation, testing and maintenance

123
Open Distributed Systems The IEC 61499 Solution
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Methodology for Distributed Applications

• 1. Obtain or develop a library of function block,
  resource and device types.
• 2. Define and develop the application.
• 3. Map function block instances from the
  application to distributed resources.
• 4. Configure devices and resources.
• 5. Configure communication connections, using
  communication service interface function blocks
  to implement the event connections and data
  connections of the application across resource
  boundaries

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Application Example Orange Sorter
126
Distributed Orange Sorter Application
127
Using Libraries
Example process/PIDD_TANK
128
A Centralized Application
129
Mapping to Distributed Devices
130
Configuring Devices (1) - Setting Parameters
131
Configuring Devices (2) - Editing Resources
132
Running the Distributed Configuration
133
Pattern Local Multicast
134
Pattern Layered MVC (Model/View/Controller)
135
Realization Simulation gt Physical Interface
136
Elements of the Engineering Architecture
137
Engineering Methodology

• 1. Sketch describe the problem to be solved.
• 2. Develop test Views.
• 3. Animate the desired operational sequences.
• 4. Develop test Models.
• 5. Develop test Controllers.
• 6. Develop test Diagnostic fault recovery
  elements.
• 7. Perform distribution design.
• 8. Integrate to physical components and systems.

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An Example
139
View Development Framework
140
Model Development Framework
141
Controller Development Framework
142
Low-Level Diagnostics
143
Distribution Design
144
Physical Design
145
Pattern Mechatronic