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WAN ZUHA WAN HASAN (UPM)

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Title: WAN ZUHA WAN HASAN (UPM)


1
THE DESIGN OF THE MEMORY BUILT-IN SELF-TEST,
DIAGNOSIS AND REPAIR (MBISTDR) FOR SRAMs
By WAN ZUHA WAN HASAN (UPM) DEPARTMENT OF
ELECTRICAL, ELECTRONIC AND SYSTEM, FACULTY OF
ENGINEERING UKM Supervised by PROF DR MASURI
OTHMAN (UKM) Co-supervisor DR BAMBANG SUNARYO
SUPARJO (MENTOR GRAPHIC USA)
2
Outline
  • Introduction
  • Memory Architecture
  • Memory Fault Models
  • Test Algorithms
  • Memory Testing, Diagnosis and Repair
  • Conclusion

3
Introduction
  • Why BIST, BISD and BISR
  • The advances of semiconductor memory
    technologies have become more complex and also
    the numbers of memory cell per chip (transistors)
    rapidly increase.
  • The ITRS 2003 has shown an ever Increasing
    percentage of chip area devoted to embedded
    memory, with todays SoCs already consisting of
    over 50 memory.

4
Introduction
5
Introduction
Memory Sizes Versus Yield
6
Introduction ITRS 2004 - SOC Test Requirements
7
Introduction The Requirement of Future MBISTDR
  • Fault Modeling New Fault Models (defect in
    deep-submicron)
  • Test algorithm design Optimal test/diagnosis
    (high defect coverage)
  • BIST allow at speed testing
  • BISR low cost repair scheme
  • ( improve the yield and reliability)

8
Memory architecture
Functional RAM Model
Source Testing and semiconductor memories, A.J.
van de Goor
9
Memory architecture
Reduced Functional RAM Model
Source Testing and semiconductor memories, A.J.
van de Goor
10
Memory Fault Models
Source Testing and semiconductor memories, A.J.
van de Goor
11
Memory Fault Models
Source Testing and semiconductor memories, A.J.
van de Goor
12
Memory Fault Models
13
Memory Fault Models
14
Memory Fault Models
15
Memory Fault Models Coupling Fault(CF)
16
Memory Fault Models Two Cell Faults - cont
17
Memory Fault Models
18
Memory Fault Models
19
Memory Fault Models Coupling Fault
Source Testing and semiconductor memories, A.J.
van de Goor
20
Memory Fault Models
21
Memory Fault Models
22
Memory Fault Models
23
Test AlgorithmsFunctional RAM Testing
  • Traditional Test
  • - Zero-One - SAF
  • - Checkerboard - SAF
  • - GALPAT and Walking 1/0 AF,
  • SAF, TF and CF - testing time
  • unacceptable
  • - Sliding Diagonal SAF, TF
  • - Butterfly SAF, AF

Source Testing and semiconductor memories, A.J.
van de Goor
24
Test AlgorithmsMarch Test Algorithms
25
Test Algorithms March Test Algorithms
26
Test Algorithms March Test Notation
Source Testing and semiconductor memories, A.J.
van de Goor
27
Test Algorithms March Test Notation
Source Testing and semiconductor memories, A.J.
van de Goor
28
Test Algorithms
Source Testing and semiconductor memories, A.J.
van de Goor
29
Test Algorithms Comparison of March Tests
Source Testing and semiconductor memories, A.J.
van de Goor
30
Test AlgorithmsFault detection using March C-
M0 M1 M2
M3 ?(w0) ? (r0, w1) ? (r1, w0) ? (r0,w1)
M4 M5 ? (r1, w0) ?(r0 - 10N Test
algorithm Disable RAM (wait) ? (r0, w1,)
Disable RAM(wait) ? (r1) - Data retention
fault(DRF)
31
Test AlgorithmsFault detection using Extended
March C- (covered SOF)
M0 M1 M2
M3 ?(w0) ? (r0, w1,r1) ? (r1, w0) ? (r0,w1)
M4 M5 ? (r1, w0) ?(r0) - 11N
Test algorithm Disable RAM (wait) ? (r0, w1,)
Disable RAM(wait) ? (r1) - Data retention
fault(DRF)
32
Test AlgorithmsFault detection using extended
March C-
Fault March Elements March Elements March Elements March Elements March Elements March Elements
Fault M0 ?(w0) M1 ?(r0, w1,r1) M2 ?(r1, w0) M3 ?(r0,w1) M4 ?(r1, w0) M5 ?(r0)
SAF I N I T I A L Z A T I O N r0 s-a-1 r1 s-a-0
TF I N I T I A L Z A T I O N M1(r0,w1) followed M2(r1,w0) followed by M2(r1) for lt?/0gt by M3(r0) for lt?/1gt M1(r0,w1) followed M2(r1,w0) followed by M2(r1) for lt?/0gt by M3(r0) for lt?/1gt M1(r0,w1) followed M2(r1,w0) followed by M2(r1) for lt?/0gt by M3(r0) for lt?/1gt
CF I N I T I A L Z A T I O N M1(r0,w1) for Cfid lt?/1gt jlti M1 followed by M2 for Cfin lt?/?gt jgti M2(r1,w0) for Cfid lt?/0gt jlti M2(r1,w0) for Cfin lt?/?gt jgti M3(r0,w1) followed M4(r1,w0) followed by M4(r1,w0) by M5(r0) for Cfid for Cfid lt?/0gt lt?/1gt M1 M3(r0,w1) M2 M4(r1,w0) Followed by followed by M5(r0) M4(r1,w0) for for Cfin lt?/ ? gt Cfin lt?/?gt all CFids is jlti ( for jgti is similar) M3(r0,w1) followed M4(r1,w0) followed by M4(r1,w0) by M5(r0) for Cfid for Cfid lt?/0gt lt?/1gt M1 M3(r0,w1) M2 M4(r1,w0) Followed by followed by M5(r0) M4(r1,w0) for for Cfin lt?/ ? gt Cfin lt?/?gt all CFids is jlti ( for jgti is similar) M3(r0,w1) followed M4(r1,w0) followed by M4(r1,w0) by M5(r0) for Cfid for Cfid lt?/0gt lt?/1gt M1 M3(r0,w1) M2 M4(r1,w0) Followed by followed by M5(r0) M4(r1,w0) for for Cfin lt?/ ? gt Cfin lt?/?gt all CFids is jlti ( for jgti is similar)
AF I N I T I A L Z A T I O N (M1(r0, w1,r1) M2(r1, w0)) jgti, (M3(r0,w1) M4 (r1, w0)) igtj (Satisfied with known technology) (M1(r0, w1,r1) M2(r1, w0)) jgti, (M3(r0,w1) M4 (r1, w0)) igtj (Satisfied with known technology) (M1(r0, w1,r1) M2(r1, w0)) jgti, (M3(r0,w1) M4 (r1, w0)) igtj (Satisfied with known technology) (M1(r0, w1,r1) M2(r1, w0)) jgti, (M3(r0,w1) M4 (r1, w0)) igtj (Satisfied with known technology)
SOF I N I T I A L Z A T I O N r1
DRF Disable RAM (wait) ? (r0, w1,) Disable RAM(wait) ? (r1) Disable RAM (wait) ? (r0, w1,) Disable RAM(wait) ? (r1) Disable RAM (wait) ? (r0, w1,) Disable RAM(wait) ? (r1) Disable RAM (wait) ? (r0, w1,) Disable RAM(wait) ? (r1) Disable RAM (wait) ? (r0, w1,) Disable RAM(wait) ? (r1) Disable RAM (wait) ? (r0, w1,) Disable RAM(wait) ? (r1)
33
Test Algorithms Functional Fault Models for
Diagnosis
ICCAD 2000 Chi-Feng Wu
34
Test Algorithms Fault detection and diagnosis
using March CL
?(w0) ? (r0, w1,) ? (r1, w0,) ?(r1)
R0 R1
R2 ? (r0,w1) ?(r1) ?(r1, w0) ?(r0)
R3 R4 R5 R6 -12N
Test algorithm Disable RAM (wait)? (r0, w1,)
Disable RAM(wait) ? (r1) - Data retention
Fault(DRF).
35
Test Algorithms Fault detection and diagnosis by
Extended March CL
?(w0) ? (r0, w1, r1) ? (r1, w0) ?(r1) ?
R0 R1
R2 R3 (r0,w1) ?(r1) ?(r1, w0)
?(r0) R4 R5 R6
R7 -13N Test algorithm Disable RAM (wait)?
(r0, w1,) Disable RAM(wait) ? (r1)- Data
retention Fault(DRF).
36
Test Algorithms Fault syndrome for March CL
37
Test Algorithms Fault syndrome for Extended
March CL
38
Test Algorithms Existing March Test Algorithms
1. ?(w0) ?(r0, w1,) ?(r1, w0) ?(r0,w1)
?(r1, w0) - Disable RAM (wait)?(r0,w1,)
Disable RAM(wait) ?(r1) 9N test algorithm with
data retention test Rob Dekker 1988, has
covered 100 coverage of the faults under the
listed fault models.   2. ?(w0) ?(r0, w1, r1,
w0) delay ?(r0, r0) ?(w1) ?(r1, w0, r0, w1)
delay ?(r1, r1) 14N test algorithm - Said
Hamdioui 2000, has covered 100 coverage of the
faults under the listed fault models and spot
defects.
39
Test Algorithms Existing March Test Algorithms
3. ?(w0) ?(r0) delay ?(r0) ?(w1) ?(r1)
delay ?(r1) or ?(w0) ?(r0) delay ?(r0)
?(w1) ?(r1) delay ?(r1) 6N test algorithm
Baosheng Wang 2003, has reduced less than half of
the required time for the 9N test algorithm   4.
?(w0) ?(r0, w1,) ?(r1) ?(r1, w0) ?(r0)
?(r0, w1) ?(r1) ?(r1, w0) ?(r0) 13N test
algorithm V. N. Yarmolik 1996, has introduced
diagnosis capability and achieved 63.6
diagnostic resolution (SAF CF).  
40
Test Algorithms Existing March Test Algorithms
5. ?(w0) ?(r0, w1,r1, w0) ?(r0, w1) ?(r1,
w0,r0, w1) ?(r1) ?(r1, w0) ?(r0) ?(r0,
w1) ?(r1) 18N test algorithm V. N.
Yarmolik 1996, has been introduced for the
diagnosis capability and achieved
90.9diagnostic resolution (SAF CF). 6.
?(w0) ?(r0, w1, w0, w1) ?(r1, w0, r0, w1) ?
(r1, w0, w1, w0) ? (r0, w1, r1, w0) Hold ?
(r0, w1) Hold ? (r1) 20N test algorithm
I. Kim 1998, has been diagnosis capability
and achieved 59 diagnostic resolution (SAF
CF).
41
Test Algorithms Existing March Test Algorithms
7. ?(w0) ?(r0, w1,r1, w0 ) ?(r0) ?(w1)
?(r1, w0,r0, w1) ?(r1) 12N test
algorithm T. J. Bergfeld 2000, has
proposed diagnosis capability but it could only
achieve 22.7 diagnostic resolution (SAF
CF). 8. ?(w0) ?(r0, w1, r1) ?(r1) ?(r1,
w0,r0) ?(r0) ?(r0, w1, r1) ?(r1) ?(r1,
w0, r0) ?(r0) 17N test algorithm
Jin-Fu Li 1996, has introduced diagnosis
capability and achieved 100 diagnostic
resolution(SAF CF).
42
Test Algorithms Existing March Test Algorithms
9. ?(w0) ?(r0, w1,) ?(r1) ?(r1, w0) ?(r0,
w1) ?(r1) ?(r1, w0) ?(r0) 12N
test algorithm plus 3N or 4N ( for aggressor
locating) V. A. Vardanian 2002, has
introduced diagnosis capability and
achieved 100 diagnostic resolution.
43
Test Algorithms
  • STATE-OF-ART FOR TEST ALGORITHMS
  •  Optimality in term of time complexity
  • Regularity and symmetry such that the self-test
    circuit can minimize the silicon area
  • High defect coverage and diagnosis capability in
    order to increase the repair capabilities and the
    overall yield

44
Memory Testing, Diagnosis and RepairMBIST
ARCHITECTURE
45
Memory Testing, Diagnosis and RepairMBISTD
ARCHITECTURE
46
Memory Testing, Diagnosis and RepairBISTD
  • STATE-OF-ART FOR BISTD
  • Minimizing BIST overhead in both silicon area and
    routing
  • Supporting diagnosis capabilities
  • Supporting different kinds of memories
    (single-port, multi-port)

47
Memory Testing, Diagnosis and RepairMBISTDR
ARCHITECTURE
48
Conclusion
MBISTDR is essential for memory reliability in
the near future. The addition of BISD and BISR
will enhance the yields of overall memory
chips. New test algorithm and fault syndromes
base on March CL has been proposed to detect and
diagnose SOF and AF.
49
  • THANK YOU
  • Q A

50
  • THANK YOU
  • Q A

51
  • THANK YOU
  • Q A

52
Memory Testing, Diagnosis and Repair Example of
MBISR
53
Memory Testing, Diagnosis and Repair
  • The Figure above shows the MBIST and Self-Repair
    using redundancy logic and Fuse Box concept.
  • The MBISR concept contains an interface between
    MBIST logic, redundancy wrapper logic to replace
    defect address and Fuse boxes to store the
    failling addresses

54
On Going Research
The design and simulation of MBISTDR . New
Test Algorithms with Diagnosis capability will be
designed according to the required coverage and
testing time.
55
MBISTDR Methodology
d_in
12
addr
bistr_data_write
12
5
MUX_1
bistr_en
mode_sel
12
5
Bistr_error_addr
MBISTDR CONTROLLER
32 X 12 SRAM
Bistr_addr
5
clk
Wr_en
Rd_en
Sram_error
12
Mode_sel
MUX_2
bistr_data_read
5
12
d_out
Design of MBISTDR Controller for Stuck-at Faults
56
MBISTDR Methodology
The schematic of MBISTDR Controller for Stuck-at
Faults
57
MBISTDR Methodology
  • Figure above shows that MBISTDR contains MBISTDR
    controller and 32x12 SRAM
  • Test Pattern In Bistr_data_write (w0/w1)
  • Mode_sel test or normal mode Enable the Wr_en
    or Rd_en
  • Test Pattern Out Bistr_data_read(r0/r1)

58
Test and Repair Algorithm of MBISTDR controller
for Stuck-at Faults
MBISTDR Methodology
59
MBISTDR Methodology
  • Figure above Shows that, how MBISTR controller
    implements the test and repair algorithm to the
    32x12 SRAM memory.
  • Procedure
  • address 1 w0 then compare with r0
  • address 2 w1 then compare with r1
  • Run until either marked addresses or
  • memory addresses reach the maximum

60
MBISTDR Results And Discussion
Fault Free Results for MBISTDR During Normal mode
Operation
61
MBISTDR Result And Discussion
Fault Detection Results for MBISTDR during Test
mode Operation
62
MBISTDR Result And Discussion
Results for MBISTDR During Normal Mode and Test
Mode Operation
63
Final Target for MBISTDR
  • Criteria
  • TA
  • High defect coverage and diagnosis capability in
    order to increase the repair capabilities and the
    overall yield below 17N
  • BISTDR
  • 1)Supporting diagnosis capabilities 100
    diagnosis resolution (include SOF and AF)
  • 2) Using Extra Memory for the BISR

64
MBISTDR Conclusion
A new memory Built-in Self-test and Repair
concept has been designed and this concept is
proposed without using any extra rows and
columns. These test and repair are only focused
on the reconfiguration of the memory addresses,
which means no extra spaces needed as the
previous researches.
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