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PPT – Introduction to CMOS VLSI Design Lecture 11: Adders PowerPoint presentation | free to download - id: 5e290c-NmMwN

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Introduction toCMOS VLSIDesignLecture 11

Adders

- David Harris
- Harvey Mudd College
- Spring 2004

Outline

- Single-bit Addition
- Carry-Ripple Adder
- Carry-Skip Adder
- Carry-Lookahead Adder
- Carry-Select Adder
- Carry-Increment Adder
- Tree Adder

Single-Bit Addition

- Half Adder Full Adder

A B Cout S

0 0

0 1

1 0

1 1

A B C Cout S

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Single-Bit Addition

- Half Adder Full Adder

A B Cout S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A B C Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

PGK

- For a full adder, define what happens to carries
- Generate Cout 1 independent of C
- G
- Propagate Cout C
- P
- Kill Cout 0 independent of C
- K

PGK

- For a full adder, define what happens to carries
- Generate Cout 1 independent of C
- G A B
- Propagate Cout C
- P A ? B
- Kill Cout 0 independent of C
- K A B

Full Adder Design I

- Brute force implementation from eqns

Full Adder Design II

- Factor S in terms of Cout
- S ABC (A B C)(Cout)
- Critical path is usually C to Cout in ripple

adder

Layout

- Clever layout circumvents usual line of diffusion
- Use wide transistors on critical path
- Eliminate output inverters

Full Adder Design III

- Complementary Pass Transistor Logic (CPL)
- Slightly faster, but more area

Full Adder Design IV

- Dual-rail domino
- Very fast, but large and power hungry
- Used in very fast multipliers

Carry Propagate Adders

- N-bit adder called CPA
- Each sum bit depends on all previous carries
- How do we compute all these carries quickly?

Carry-Ripple Adder

- Simplest design cascade full adders
- Critical path goes from Cin to Cout
- Design full adder to have fast carry delay

Inversions

- Critical path passes through majority gate
- Built from minority inverter
- Eliminate inverter and use inverting full adder

Generate / Propagate

- Equations often factored into G and P
- Generate and propagate for groups spanning ij
- Base case
- Sum

Generate / Propagate

- Equations often factored into G and P
- Generate and propagate for groups spanning ij
- Base case
- Sum

Valency-2 equation uses P/G of two smaller groups

Gi-10 is simply the carry-in of this stage, ie.,

Ci Si Pi xor Ci (Ai xor Bi) xor Ci

PG Logic

C4 G4 P4 G30

Carry-Ripple Revisited

Note Carry propagates through And/or network

instead of MAJ gate network

Carry-Ripple PG Diagram

Carry-Ripple PG Diagram

1-bit prop/gen cell

delay of And/OR in grey cell

Final SUM bit xor

PG Diagram Notation

Generate only

Both Gen/Prop

Carry-Skip Adder

- Carry-ripple is slow through all N stages
- Carry-skip allows carry to skip over groups of n

bits - Decision based on n-bit propagate signal

Critical path Generate carry in first bit, then

ripple thru next three bits. Then skip next two

four-bit stages, then ripple through last stage.

Carry-Skip PG Diagram

- For k n-bit groups (N nk)

Carry-Skip PG Diagram

- For k n-bit groups (N nk)

First, last group ripple

skip thru muxes

Variable Group Size

Delay grows as O(sqrt(N))

Smaller groups at first/last

Carry-Lookahead Adder

- Carry-lookahead adder computes Gi0 for many bits

in parallel. - Uses higher-valency cells with more than two

inputs.

CLA PG Diagram

Collecting Generate/Propagate over many cells

Higher-Valency Cells

Just the recursive definition of Generate

Carry-Select Adder

- Trick for critical paths dependent on late input

X - Precompute two possible outputs for X 0, 1
- Select proper output when X arrives
- Carry-select adder precomputes n-bit sums
- For both possible carries into n-bit group

Carry Select Critical Path

N adder size in each group, K groups

Tselect Tpg N(K-2)TAO Tmux

Slightly faster than Carry-skip. For optimal

delay, do not want each group to have the same

size, want each group to grow in order to match

mux select arrival time with carry generation

time.

Carry-Increment Adder

- Factor initial PG and final XOR out of

carry-select

Carry-Increment Adder

- Factor initial PG and final XOR out of

carry-select

Adders in Carry-select have redundant logic,

factor this out, reduces logic size, delay

essentially the same.

Variable Group Size

- Also buffer
- noncritical
- signals

Observe that buffer is added so that buffer delay

is not on critical path!

Tree Adder

- If lookahead is good, lookahead across lookahead!
- Recursive lookahead gives O(log N) delay
- Many variations on tree adders

Brent-Kung

Buffers not really necessary

Lots of logic levels!

Sklansky

High Fanout

Kogge-Stone

Lots-o-wires

Tree Adder Taxonomy

- Ideal N-bit tree adder would have
- L log N logic levels
- Fanout never exceeding 2
- No more than one wiring track between levels
- Describe adder with 3-D taxonomy (l, f, t)
- Logic levels L l
- Fanout 2f 1
- Wiring tracks 2t
- Known tree adders sit on plane defined by
- l f t L-1

Tree Adder Taxonomy

Tree Adder Taxonomy

Logic levels

Fanout

Wire tracks

Han-Carlson

Knowles 2, 1, 1, 1

Half the wires at last stage than Kogge-Stone,

but double the loading.

Ladner-Fischer

Taxonomy Revisited

Hybrid Tree/Carry Select

- Hybrid adders use tree-logic to compute the

carries, but also use short ripple chains to

reduce the number of gates - Fig 10.39 of the book shows a good example of a

sparse tree adder

Summary

Adder architectures offer area / power / delay

tradeoffs. Choose the best one for your

application.

Architecture Classification Logic Levels Max Fanout Tracks Cells

Carry-Ripple N-1 1 1 N

Carry-Skip n4 N/4 5 2 1 1.25N

Carry-Inc. n4 N/4 2 4 1 2N

Brent-Kung (L-1, 0, 0) 2log2N 1 2 1 2N

Sklansky (0, L-1, 0) log2N N/2 1 1 0.5 Nlog2N

Kogge-Stone (0, 0, L-1) log2N 2 N/2 Nlog2N

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