Stefanos Skoulaxinos

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Reliable SW/HW Co-Design for Wireless
Communication System Integrating the Spin Model
Checker and Celoxica's DK Suite

• Stefanos Skoulaxinos
• School of EPS School of MACS
• Heriot-Watt University, Edinburgh

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Roadmap

• SW-HW Co-Design, Rules and Dangers
• The Wireless Communication System Long Range
  Identification Tag (LRID)
• Expected System Survivability
• Reliability Enhancement Strategies
• Implementation Targeted FPGA Platform
• Testing Procedure
• Analysis of Results and Reliability Estimation
• Work in progress 3d Tag Location

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SW-HW Co-Design a trip from idealism to
realism
Dangers 1 Irrational Abstraction Raising the
design level at a theoretical and impractical
level for targeted application 2 Flawed
Synthesis process
Potential 1 Increased system readability and
testability, fast code turn-arounds,
impressive productivity gains 2 Bridging the gap
between software and hardware development methods
and tools 3 Application of high level
reliability enhancement strategies 4 Level of
abstraction can lift the designer seat enabling
more complex applications through a more
testable development process 5 Possibility of
monitoring and healing system defects (SW or HW)
through a multi- layered software architecture
(Operating System). Lower levels of fault
tolerance (TMR) can be synthesized by the
Compiler automatically.
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LRID Tag - Overview
Requirements

• Tolerate environmental noise
• Self monitor and heal
• Increased levels of survivability
• Minimal power consumption at remote station
• Maximal processing accuracy at base station

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LRID Tag Main Operation
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LRID Tag Task Overhead
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Software Reliability Enhancement Strategies

• 1 Fault Prevention __
• High Quality Specification
• Design Diversity
• Modeling, Formal Verification
• Testing
• Structured Design Principles

Applied to the Tag
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• 2 Fault Tolerance __
• Run Time monitoring (Watchdog Timers)
• Fault Location and Isolation
• SW/HW Redundancy
• N-Version Programming, Voting Schemes

Applied to the Tag
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Fault Prevention Modeling and Formal
Verification
Aiming for high levels of reliability, it is
essential to understand the system in depth.
Modeling provides an alternative view of the
design and thus contributing to this process.
Formal verification following modeling is
an exhaustive computer based verification
covering all possible event scenarios
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Applied to the Tag
The Tag was Modelled and Verified in the Spin
Model Checker
Spin is considered one of the most efficient
software verification tools currently available.
It is actively used in safety critical NASA
applications such as the application to Cassini
(mission to Saturn) and the Mars Pathfinder.
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Fault Prevention Structured Design
A set of guidelines which need to be followed by
system designers. It can contribute to code
readability and testability, making
fault-removal processes easier and more effective
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Applied to the Tag
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Fault Tolerance Run-time Monitoring
Software or hardware redundancy aiming to monitor
run time operation of the main system. It is
commonly used in high end safety critical
applications including NASA missions. In such
complex systems, monitoring tends to form
multilayered architectures covering both
Software and Hardware fault scenarios
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Applied to the Tag
We have developed Watchdog timers and
Forward Error correction (FEC) architectures. We
have taken the proven watchdog timer scheme a
step further by introducing access points and
multilayered implementation. We have developed
FEC schemes to counterbalance expected medium
noise
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Run Time Monitoring Watchdog Timers
-Watchdog Timers are monitoring architectures
utilised to detect if a system has deadlocked
-Can cover a wide range of faults including
software, hardware and real time bugs
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Run Time Monitoring Watchdog Timers
Example of Multi-layered Implementation
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FPGA platforms utilized during Testing
-utilized to control data communication with
user PC, ID reception from antenna and tag
location computations, all processes executed in
parallel -capable of correlating multiple IDs in
a truly concurrent manner -100 MHz on board
oscillator -can deploy 32 MB of on board
SDRAM -the Spartan IIE board supports 3.3V and
2.5V I/O standards
-Optimized for very low power high performance
systems, ideal for wireless applications -On
board low power oscillator set at 32kHz -the
board supports 1.8V and 3.3V I/O standards
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Testing Procedure
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Analysis of Results Reliability Estimation
Notes Test Results were analysed in the CASRE
Reliability Estimation Tool (developed by
JPL-NASA)
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Work in progress 3d Tag Location
Operation 1 User activates tag location query
in the front end API (shown above) 2 API
connects with the base station hardware (Xilinx
Spartan IIE FPGA) and initiates transmission to
remote stations 3 Selected Remote stations
respond by sending their unique ID sequence. 4
Time of arrival of ID at three base station
antennas is utilized by the FPGA to compute
precise x,y and z co-ordinates of the tag. The
co-ordinates are sent back to the API, which are
displayed in a 3d animated view.
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Conclusions
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Acknowledgements
The presenter wishes to thank everyone who has
contributed from the conception (2002) and
development of the research project . The
Dependable Systems Group and Microengineering
Group in Heriot-Watt University, as well as the
Institute for System Level Integration (ISLI) and
Scottish Embedded Software Centre (SESC) in
Livingston.
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