Hardware / Software Codesign Term Project : (1)AMBA BUS (2)Integration ARM and RTOS

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Hardware / Software Codesign Term Project
(1)AMBA BUS (2)Integration ARM and RTOS

• D90522024 ???
• F91522803 ???

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Agenda

• Why Need HW/SW Co-design?
• What is our first step?
• AMBA BUS
• Conclusion 1
• ARM ADS and RTOS Integration
• Conclusion 2

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Why Need HW/SW Co-design?

• IC design has ushered in a new era SoC
• System on a Chip

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Why Need HW/SW Co-design?

• What is SoC?

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Why Need HW/SW Co-design?

• What is our first step?
• Processor?
• Memory?
• Operating System?
• Peripheral Interface?
• CAD Tools?
• What else?

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What is our first step?

• Core IP (Processor)
• PC Workstation
• Intel Pentium
• Ultra SPARC
• MIPS
• Micro-Controller
• 8051
• DSP
• TI,
• SoC
• ARM
• Power PC
• Configurable Tensilica Processor
• SOPC
• Altera Nios
• Xillinx Micro-Blaze
• Is there any opportunity for us in this area?

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What is our first step?

• Memories Design is our chance?
• Process?
• Operating System is another opportunity?
• PC Workstation
• Windows
• Unix Solaris, HP-Unix
• Linux
• RTOS
• eCos
• Micrium ?uC/OSII
• Shugyo Design ? KROS
• Accelerated Technology ? Nucleus Plus
• VxWork
• Embedded System
• Windows CE
• uCLinux

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What is our first step?

• Peripheral IP Design is one way for us?
• PrimeCell ARM
• Synopsys
• FPGA Vendor --
• Open Core Web Site www.opencores.org
• . . .
• EDA CAD Tool?
• Cadence
• Synopsys
• Mentor
• ????

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(No Transcript)
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What is our first step?

• Can We Find Our Way in SoC or HW/SW Co-design
  Era?
• Master in applications
• ASIC
• SW
• Time to Market is another important thing
• Use Well-Design IP
• Embedded Linux, RTOS
• What else?
• Integration
• System is the keyword of SoC
• How to transition from on-board design to on-chip
  design?
• AMBA Bus (One Important Issue)
• Advanced Microcontroller Bus Architecture

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AMBA BUS
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AMBA BUS
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AMBA BUS

• AMBA Buses
• Advanced System Bus (ASB)
• Advanced High-Performance Bus (AHB)
• Processors
• On-Chip Memory
• Off-Chip External Memory with low power
  peripheral macrocell
• Bridge to APB
• High Speed ASIC Your Design
• Advanced Peripheral Bus (APB)
• Peripheral Interface
• UART
• Timer
• Low Speed ASIC Your Design

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AMBA BUS

• Advanced High-Performance Bus AHB

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AMBA BUS

• Advanced High-Performance Bus AHB

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AMBA BUS ? AHB

• Advanced High-Performance Bus AHB
• AHB master is able to initiate read and write
  operations by providing an address and control
  information. Only one bus master is allowed to
  actively use the bus at any one time.(max. 16)
• AHB slave responds to a read or write operation
  within a given address-space range. The bus slave
  signals back to the active master the success,
  failure or waiting of the data transfer.
• AHB arbiter ensures that only one bus master at a
  time is allowed to initiate data transfers.
• AHB decoder is used to decode the address of each
  transfer and provide a select signal for the
  slave that is involved in the transfer. A single
  centralized decoder is required in all AHB
  implementations.

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AMBA BUS ? AHB
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AMBA BUS ? AHB
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AMBA BUS ? AHB

• Basic Transfer of AHB

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AMBA BUS ? AHB

• Transfer Types of AHB

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AMBA BUS ? AHB

• Burst Operation of AHB

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AMBA BUS ? AHB

• Incrementing bursts access sequential locations
  and the address of each transfer in the burst is
  just an increment of the previous address.
• An incrementing burst can be of any length, but
  the upper limit is set by the fact that the
  address must not cross a 1kB boundary
• For wrapping bursts, if the start address of the
  transfer is not aligned to the total number of
  bytes in the burst (size x beats) then the
  address of the transfers in the burst will wrap
  when the boundary is reached. For example, a
  four-beat wrapping burst of word (4-byte)
  accesses will wrap at 16-byte boundaries.
  Therefore, if the start address of the transfer
  is 0x34, then it consists of four transfers to
  addresses 0x34, 0x38, 0x3C and 0x30.

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AMBA BUS ? AHB

• There are certain circumstances when a burst will
  not be allowed to complete and therefore it is
  important that any slave design which makes use
  of the burst information can take the correct
  course of action if the burst is terminated
  early. The slave can determine when a burst has
  terminated early by monitoring the HTRANS signals
  and ensuring that after the start of the burst
  every transfer is labelled as SEQUENTIAL or BUSY.
  If a NONSEQUENTIAL or IDLE transfer occurs then
  this indicates that a new burst has started and
  therefore the previous one must have been
  terminated.

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AMBA BUS ? AHB
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AMBA BUS ? AHB
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AMBA BUS ? AHB

• HSIZE20 of AHB

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AMBA BUS ? AHB

• The protection control signals, HPROT30 of AHB

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AMBA BUS ? AHB

• AHB Bus Slave

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AMBA BUS ? AHB

• AHB Bus Master

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AMBA BUS ? AHB

• AHB Arbiter

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AMBA BUS ? AHB

• AHB Decoder

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AMBA BUS ? APB

• Advanced Peripheral Bus APB
• The AMBA APB should be used to interface to any
  peripherals which are lowbandwidth and do not
  require the high performance of a pipelined bus
  interface.

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AMBA BUS ? APB
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AMBA BUS ? APB

• IDLE
• The default state for the peripheral bus.
• SETUP
• When a transfer is required the bus moves into
  the SETUP state, where the appropriate select
  signal, PSELx, is asserted. The bus only remains
  in the SETUP state for one clock cycle and will
  always move to the ENABLE state on the next
  rising edge of the clock.
• ENABLE
• In the ENABLE state the enable signal, PENABLE is
  asserted. The address, write and select signals
  all remain stable during the transition from the
  SETUP to ENABLE state. The ENABLE state also only
  lasts for a single clock cycle and after this
  state the bus will return to the IDLE state if no
  further transfers are required. Alternatively, if
  another transfer is to follow then the bus will
  move directly to the SETUP state. It is
  acceptable for the address, write and select
  signals to glitch during a transition from the
  ENABLE to SETUP states.

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AMBA BUS ? APB

• Write Transfer of APB

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AMBA BUS ? APB

• Read Transfer of APB

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AMBA BUS ? APB

• APB Bridge

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AMBA BUS ? APB

• APB Slave

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Conclusion

• What do you want in SoC era?

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(2)Integrate uC/OS-II into ARM Development Suite
(ADS)

• D90522024 ???
• F91522803 ???

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• Introduction to ADS
• Experiment 1
• Analysis of ARM and Thumb instruction
• Experiment 2
• Integrate UC/OSII into ADS

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ARM Development Suite (ADS)

• Project management
• Configuring the settings of build targets for
  project

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The Structure of ARM Tools
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Main components of ADS

• ANSI C compilers- armcc, tcc
• ISO/Embedded C compilers armcpp, tcpp
• ARM/Thumb assembler- armasm
• Linker armlink
• Project management tool CodeWarrior
• Instruction set simulator ARMulator
• Debuggers AXD, ADW, ADU and armsd
• Format converter fromelf
• Libarian armar
• ARM profiler armprof

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CodeWarrier

• Provides a simple, versatile graphical user
  interface for managing your software development
  projects
• Develop C,C, and ARM assembly language code
• Targeted at ARM and Thumb processors

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Project File View
Create New Project
Target Setting
Editor Window
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AXD

• Various views allow you to examine and control
  the processes you are debugging

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ARMulator

• A suite of programs that models the behavior of
  various ARM processor cores and system
  architecture in software on a host system
• Can be operates at various levels of accuracy
• Instruction accurate
• Cycle accurate
• Timing accurate
• Benchmarking before hardware is available

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• Introduction to ADS
• Experiment 1
• Analysis of ARM and Thumb instruction
• Experiment 2
• Integrate UC/OSII into ADS

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Analysis of ARM and Thumb instruction(1/8)
ARM and Thumb code size
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Analysis of ARM and Thumb instruction(2/8)
The need for interworking

• The code density of Thumb and its performance
  from narrow memory make it ideal for the bulk of
  C code in many systems. However there is still a
  need to change between ARM and Thumb state within
  most applications
• ARM code provides better performance from wide
  memory
• Some functions can be performed with ARM
  instructions
• Thumb programs will also need an ARM assembler
  header to change state and call the Thumb routine

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Analysis of ARM and Thumb instruction(3/8)
ARM/Thumb Interworking using ASM (no Veneer)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AREA AddReg,CODE,READONLY Name this block of code. ENTRY Mark first instruction to call. Main ADR r0,ThumbProg 1 Generate branch target address and set bit 0,hence arrive at target in Thumb state. BX r0 Branch exchange to ThumbProg. CODE16 Subsequent instructions are Thumb code. ThumbProg MOV r2,2 Load r2 with value 2. MOV r3,3 Load r3 with value 3. ADD r2,r2,r3 r2 r2 r3 ADR r0,ARMProg BX r0 CODE32 Subsequent instructions are ARM code. ARMProg MOV r4,4 MOV r5,5 ADD r4,r4,r5 Stop MOV r0,0x18 angel_SWIreason_ReportException LDR r1,0x20026 ADP_Stopped_ApplicationExit SWI 0x123456 ARM semihosting SWI END Mark end of this file.
ARM State
Thumb State
ARM State
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Analysis of ARM and Thumb instruction(4/8)
ARM/Thumb interworking using ASM (using Veneer)
Arm.s
1 2 3 4 5 6 7 8 9 10 11 12 AREA Arm,CODE,READONLY Name this block of code. IMPORT ThumbProg ENTRY Mark 1st instruction to call. ARMProg MOV r0,1 Set r0 to show in ARM code. BL ThumbProg Call Thumb subroutine. MOV r2,3 Set r2 to show returned to ARM. Terminate execution. MOV r0,0x18 angel_SWIreason_ReportException LDR r1,0x20026 ADP_Stopped_ApplicationExit SWI 0x123456 ARM semihosting SWI END

Thumb.s
1 2 3 4 5 6 7 AREA Thumb,CODE,READONLY Name this block of code. CODE16 Subsequent instructions are Thumb. EXPORT ThumbProg ThumbProg MOV r1,2 Set r1 to show reached Thumb code. BX lr Return to ARM subroutine. END Mark end of this file.
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Analysis of ARM and Thumb instruction(5/8)
ARM/Thumb interworking using ASM (using Veneer)
armsd list 0x8000 ArmProg 0x00008000
0xe3a00001 .... gt mov r0,1 0x00008004
0xeb000005 .... bl VenATThumbProg 0x000080
08 0xe3a02003 . .. mov r2,3 0x0000800c
0xe3a00018 .... mov r0,0x18 0x00008010
0xe59f1000 .... ldr r1,0x00008018
0x00020026 0x00008014 0xef123456 V4.. swi 0x123
456 0x00008018 0x00020026 ...
dcd 0x00020026 ... ThumbProg 0000 0x0000801c
0x2102 .! mov r1,2 0002 0x0000801e
0x4770 pG bx r14 VenATThumbProg 0000 0x000
08020 0xe59fc000 .... ldr r12,0x00008028
0x0000801d 0004 0x00008024 0xe12fff1c ../.
bx r12 0008 0x00008028 0x0000801d ....
dcd 0x0000801d .... 000c 0x0000802c
0xe800e800 .... dcd 0xe800e800 .... 0010 0x000
08030 0xe7ff0010 .... dcd 0xe7ff0010 .... 001
4 0x00008034 0xe800e800 .... dcd 0xe800e800 ..
.. 0018 0x00008038 0xe7ff0010 ....
dcd 0xe7ff0010 ....
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Analysis of ARM and Thumb instruction(6/8)
ARM/Thumb interworking using C/C
armmain.c
1 2 3 4 5 6 7 8 9 10 include ltstdio.hgt extern void thumb_function(void) int main(void) printf("Hello from ARM\n") thumb_function() printf("And goodbye from ARM\n") return (0)
thumbsub.c
1 2 3 4 5 include ltstdio.hgt void thumb_function(void) printf("Hello and goodbye from Thumb\n")
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Analysis of ARM and Thumb instruction(7/8)
Timing
Analysis Tool
Code Size
Profiling
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Analysis of ARM and Thumb instruction(8/8)
Performance
FDCT (ARM Code) FDCT (Thumb Code)
Total ROM Size 25.46kB 22.13kB
Total Cycle 592782 709741
Main program profiling 9.46 9.60

• FDCT(ARM) ?????,?????
• FDCT(Thumb) ????,???????

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• Introduction to ADS
• Experiment 1
• Analysis of ARM and Thumb instruction
• Experiment 2
• Integrate UC/OSII into ADS

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µC /OS-II

• Written by Jean J. Labrosse in ANSI C
• A portable, ROMable, scalable, preemptive,
  real-time, multitasking kernel
• shipped with ARM Firmware Suite (AFS).
• Portable 8 bit64 bit
• ROMable small memory footprint
• Scalable select feature at compile time
• Multitasking preemptive scheduling, up to 64
  tasks

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Integrate µC /OS-II into ARM

• uHAL is shipped in ARM Firmware Suite
• uHAL is a basic library that enables simple
  application to run on a variety of ARM-based
  development systems
• uC/OS-II use uHAL to access ARM-based hardware

uC/OS-II user application
AFS Utilities
uHAL routines / AFS support routines
ARM-based hardware
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Resource management
To use a shared resource such as I/O port,
hardware device or global variable, you must
request the semaphore from OS and release the
semaphore after access
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Inter-Process Communication using Mailbox
In µC/OS-II, tasks are not allowed to communicate
to each other directly. The communication must be
done under control of OS through Mailbox
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Memory Management
In µC/OS-II, memory allocation is semi-dynamic.
Programmer must statically allocate a memory and
partition the region using µC/OS-II Kernel API.
Tasks can only request pre-partitioned fixed-size
memory space from µC/OS-II
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Setting up the ARMulator

• The ARMulator can function as virtual prototype
  to various ARM core and development boards.
  However, the original configuration of ARMulator
  does not match that of ARM Integrator/AP

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Building µC/OS-II

• Edit OS_CFG.C/ OS_CFG.H to customize µC/OS-II.
• Adding access path for ARMuHAL library

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Building µC/OS-II

• 3. Include uC/OS-II project and library
• 4. Include ARMuHAL project and library

ARMuHAL
uC/OS-II
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Building Program with µC/OS-II

• Create two tasks to perform inter-Process
  communication (IPC)
• Deliver the counting number by mailbox

0 1 2 3 4 5 6
lt----Task1 lt----Task2 lt----Task1 lt----Task2 lt----T
ask1 ?----Task2 ?----Task1
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Main function
/ main function / int main(int argc, char
argv) / do target (uHAL based ARM
system) initialisation / ARMTargetInit()
/ needed by uC/OS / OSInit() /
create message mailbox / Mbox12
OSMboxCreate((void) NULL) // initially, no
message from task1 to task2 Mbox21
OSMboxCreate((void) token) // initially, a
token is in mailbox so that /
create the tasks in uC/OS /
OSTaskCreate(Task1, (void )0, (void)Stack1STAC
KSIZE - 1, 4) OSTaskCreate(Task2, (void
)0, (void)Stack2STACKSIZE - 1, 3) /
Start the (uHAL based ARM system) system running
/ ARMTargetStart() / start the game
/ OSStart() / never reached /
return(0)
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void Task1(void pata) INT8U err
int info for() info
(int) OSMboxPend(Mbox21, 0, err) // wait for
task2 to complete printf("Task1 called
s\n",smileinfo)
count if(countgt6)
printf("Task1 waiting...... ") scanf("d",st
op ) // let the task1 wait for user information
OSMboxPost(Mbox12,
(void) count)
Task1
void Task2(void pdata) INT8U err
int info for() info (int)
OSMboxPend(Mbox12, 0, err) // wait message from
task1 printf("Task2 called
s\n",smileinfo) count OSMboxPost(Mbox2
1, (void) count)
Task2
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Result
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Conclusion

• As applications of the embedded systems become
  more complex, the operating system support and
  development environment became crucial. It can
  shorten the period of development. That is why we
  design the simple experiment for the project