We assume both adders are implemented with carry ripple adders. Every signal in

1
HA2
1/2
a
Given is the following circuit. The input a is
added in the first adder and subsequently in
the second adder after multiplication by ½.
4
s


4
We assume both adders are implemented with carry
ripple adders. Every signal in this example
contains 4 bits and ? represents the delay of the
carry of the full adder. The delay of the sum
output equals 2?. 1. Draw a bitlevel
representation of this circuit. 2. How long is
the critical path ? 3. What is the smallest
possible critical path that can be be obtained by
pipelining or retiming ? What is the
minimal number of flipflops ? 4. Can this circuit
be speeded up by transformations ? How long is
the critical path ? What is the minimal
number of flipflops ?
2
a3
a2
a1
a0
HA2
1/2
c0


c1




a3
a2
a1
a0
s2
s1
s0
s3


?s2?c No transform delay 7?c 4 FF Delay
loop 4?c
c0

c1

?s2?c No transform delay 5?c 10 FF






s2
s1
s0
s3
3
HA2
a3
a2
a1
a0






c0



c1



a3
a2
a1
a0
















c0



s2
s1
s0
s3




delay 4?c 22 FF latency 3
c1













s2
s1
s0
s3
delay 2?c 26 FF latency 4
4
HA3
Given are two very similar filterstructures. The
nodes M1, M2 and M3 represent data times constant
multipliers. It is assumed that the constants are
available inside the multiplication nodes.
Therefore they have only one datainput.
in
M3
M2
M1
M3
M2
in
out
out




M1

• Represent both graphs using the graph model we
  discussed.
• Perform the different steps according to the
  first multiplexing method
• allocation, assignment, merging, retime or
  pipeline and interconnect optimisation.
• Assume that the critical path is equal to one
  multiplication one adder.
• Assume that the input and output nodes have
  zero delay.
• Minimize the number of flipflops and the number
  of multiplexers.
• Can the result be improved by doing retiming
  before merging ?

5
HA3
2
2
1
M3
M2
M3
M2
1
in
M1
in
out
out




M1
2
2
merging
1
M3
M2
1
in
out


M1
6
HA3
2
2
1
M3
M2
1
in
out


M1
2
1
M2
M3
1
M3
M2
0
1
1

out

in
M1
in
out


M1
1
M2
M3
out


in
M1
7
HA3 retiming before merging
2
2
1
M3
M2
M3
M2
1
in
M1
in
out
out




M1
2
1
1
M3
M2
M3
M2
1
1
1
1
in
M1
in
out
out




M1
2
1
1
M3
M2
0
1
M2
M3
in
out


M1
1
out

in
M1

8
HA4
Given is the following biquad filter. All signals
are 4 bits wide. Design a bitserial
implementation with a multiplexfactor R
4. Indicate the clockcycles at which the input
bits are consumed and the output bits are
produced.
x(f)
y(f)
z-1
y(f-1)
z-1
y(f-2)
9
x(f)
y(f)
HA4
z-1
c0
y(f-1)
x
z-1
c1
y(f-2)
y
c0
x
c1
y
10
x(f)
y(f)
HA4
z-1
y(f-1)
z-1
y(f-2)
c0
x3
y3
x
x2
y2
c1
x1
y1
y
x0
y0