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Memories: RAM, ROM Advanced Testbenches

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Title: Memories: RAM, ROM Advanced Testbenches

1
Memories RAM, ROMAdvanced Testbenches
ECE 545 Lecture 7
2
Sources Required Reading

Volnei A. Pedroni, Circuit Design with VHDL
Chapter 9.10, Memory Design
Chapter 7.1, Constant
Chapter 3.6, Records
Chapter 11.6, Assert
Sundar Rajan, Essential VHDL RTL Synthesis Done
Right
Chapter 14, starting from Design Verification

3
Generic Memories
4
Generic RAM (1)

LIBRARY ieee
USE ieee.std_logic_1164.all
--------------------------------------------------
-----------------------------------------------
ENTITY ram IS
GENERIC (bits INTEGER8 -- of bits
per word
words INTEGER 16) --
of words in the memory
PORT (wr_ena, clk IN STD_LOGIC
addr IN INTEGER RANGE 0 to words-1
data_in IN STD_LOGIC_VECTOR(bit
s -1 downto 0)
data_out OUT STD_LOGIC_VECTOR(bits 1
downto 0)
)
END ram

5
Generic RAM (2)

ARCHITECTURE behavioral OF ram IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits 1 DOWNTO 0)
SIGNAL memory vector array
BEGIN
PROCESS(clk)
BEGIN
IF(wr_ena1) THEN
IF (clkEVENT AND clk1) THEN
memory(addr) lt data_in
END_IF
END IF
END PROCESS
data_out lt memory(addr)
END ram

6
Generic ROM (1)

LIBRARY ieee
USE ieee.std_logic_1164.all
--------------------------------------------------
-----------------------------------------------
ENTITY rom IS
GENERIC (bits INTEGER8 -- of bits
per word
words INTEGER 8)
-- of words in the memory
PORT ( addr IN INTEGER RANGE 0 to
words-1
data OUT STD_LOGIC_VECTOR(bits 1 downto
0)
)
END rom

7
Generic ROM (2)

ARCHITECTURE behavioral OF rom IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits 1 DOWNTO 0)
CONSTANT memory vector_array
("0000_0000",
"0000_0010",
"0000_0100",
"0000_1000",
"0001_0000",
"0010_0000",
"0100_0000",
"1000_0000")
BEGIN
data lt memory(addr)
END rom

8
Generic ROM (3) hexadecimal notation

ARCHITECTURE behavioral OF rom IS
TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR(bits 1 DOWNTO 0)
CONSTANT memory vector_array
(X"00",
X"02",
X"04",
X"08",
X"10",
X"20",
X"40",
X"80")
BEGIN
data lt memory(addr)
END rom

9
FPGA specific memories
10
Distributed RAM

CLB LUT configurable as Distributed RAM
A LUT equals 16x1 RAM
Implements Single and Dual-Ports
Cascade LUTs to increase RAM size
Synchronous write
Synchronous/Asynchronous read
Accompanying flip-flops used for synchronous read

11
RAM 16x1 (1)

library IEEE
use IEEE.STD_LOGIC_1164.all
library UNISIM
use UNISIM.all
entity RAM_16X1_DISTRIBUTED is
port(
CLK in STD_LOGIC
WE in STD_LOGIC
ADDR in STD_LOGIC_VECTOR(3 downto 0)
DATA_IN in STD_LOGIC
DATA_OUT out STD_LOGIC
)
end RAM_16X1_DISTRIBUTED

12
RAM 16x1 (2)

architecture RAM_16X1_DISTRIBUTED_STRUCTURAL of
RAM_16X1_DISTRIBUTED is
-- part used by the synthesis tool, Synplify Pro,
only ignored during simulation
attribute INIT string
attribute INIT of RAM16X1_S_1 label is "0000"
--------------------------------------------------
----------------------
component ram16x1s
generic(
INIT BIT_VECTOR(15 downto 0) X"0000")
port(
O out std_ulogic
A0 in std_ulogic
A1 in std_ulogic
A2 in std_ulogic
A3 in std_ulogic
D in std_ulogic
WCLK in std_ulogic
WE in std_ulogic)
end component

13
RAM 16x1 (3)

begin
RAM_16X1_S_1 ram16x1s generic map (INIT gt
X0000")
port map
(O gt DATA_OUT,
A0 gt ADDR(0),
A1 gt ADDR(1),
A2 gt ADDR(2),
A3 gt ADDR(3),
D gt DATA_IN,
WCLK gt CLK,
WE gt WE
)
end RAM_16X1_DISTRIBUTED_STRUCTURAL

14
RAM 16x8 (1)

library IEEE
use IEEE.STD_LOGIC_1164.all
library UNISIM
use UNISIM.all
entity RAM_16X8_DISTRIBUTED is
port(
CLK in STD_LOGIC
WE in STD_LOGIC
ADDR in STD_LOGIC_VECTOR(3 downto 0)
DATA_IN in STD_LOGIC_VECTOR(7 downto 0)
DATA_OUT out STD_LOGIC_VECTOR(7 downto 0)
)
end RAM_16X8_DISTRIBUTED

15
RAM 16x8 (2)

architecture RAM_16X8_DISTRIBUTED_STRUCTURAL of
RAM_16X8_DISTRIBUTED is
attribute INIT string
attribute INIT of RAM16X1_S_1 label is "0000"
component ram16x1s
generic(
INIT BIT_VECTOR(15 downto 0) X"0000")
port(
O out std_ulogic
A0 in std_ulogic
A1 in std_ulogic
A2 in std_ulogic
A3 in std_ulogic
D in std_ulogic
WCLK in std_ulogic
WE in std_ulogic)
end component

16
RAM 16x8 (3)

begin
GENERATE_MEMORY
for I in 0 to 7 generate
RAM_16X1_S_1 ram16x1s
generic map (INIT gt X"0000")
port map
(O gt DATA_OUT(I),
A0 gt ADDR(0),
A1 gt ADDR(1),
A2 gt ADDR(2),
A3 gt ADDR(3),
D gt DATA_IN(I),
WCLK gt CLK,
WE gt WE
)
end generate
end RAM_16X8_DISTRIBUTED_STRUCTURAL

17
ROM 16x1 (1)

library IEEE
use IEEE.STD_LOGIC_1164.all
library UNISIM
use UNISIM.all
entity ROM_16X1_DISTRIBUTED is
port(
ADDR in STD_LOGIC_VECTOR(3 downto 0)
DATA_OUT out STD_LOGIC
)
end ROM_16X1_DISTRIBUTED

18
ROM 16x1 (2)

architecture ROM_16X1_DISTRIBUTED_STRUCTURAL of
ROM_16X1_DISTRIBUTED is
attribute INIT string
attribute INIT of ROM16X1_S_1 label is "F0C1"
component ram16x1s
generic(
INIT BIT_VECTOR(15 downto 0) X"0000")
port(
O out std_ulogic
A0 in std_ulogic
A1 in std_ulogic
A2 in std_ulogic
A3 in std_ulogic
D in std_ulogic
WCLK in std_ulogic
WE in std_ulogic)
end component

19
ROM 16x1 (3)

begin
ROM_16X1_S_1 ram16x1s
generic map (INIT gt X"F0C1")
port map
(OgtDATA_OUT,
A0gtADDR(0),
A1gtADDR(1),
A2gtADDR(2),
A3gtADDR(3),
DgtLow,
WCLKgtLow,
WEgtLow
)
end ROM_16X1_DISTRIBUTED_STRUCTURAL

20
std_logic vs. std_ulogic

TYPE std_ulogic IS
(U, X, 0, 1, Z, W, L, H,
-)
SUBTYPE std_logic IS std_ulogic
RANGE X TO -

21
Conversion std_ulogic_vector gt integer

LIBRARY ieee
USE ieee.std_logic_1164.all
.........
SIGNAL i INTEGER
SIGNAL su STD_ULOGIC_VECTOR(7 DOWNTO 0)
..........
i lt conv_integer(su)

22
Constants
23
Constants

Syntax
CONSTANT name type value
Examples
CONSTANT high STD_LOGIC 1
CONSTANT datamemory memory
((X"00",
X"02")

24
Constants - features

Constants can be declared in a
PACKAGE, ENTITY, ARCHITECTURE
When declared in a PACKAGE, the constant
is truly global, for the package can be used
in several entities.
When declared in an ARCHITECTURE, the
constant is local, i.e., it is visible only
within this architecture.
When declared in an ENTITY, the constant can be
used in
all architectures associated with this entity.

25
Specifying time in VHDL
26
Physical data types

Types representing physical quantities, such
as time, voltage, capacitance, etc. are referred
in VHDL as physical data types.
TIME is the only predefined physical data
type.
Value of the physical data type is called a
physical literal.

27
Time values (physical literals) - Examples

7 ns
1 min
min
10.65 us
10.65 fs

Space
Numeric value
Unit of time (dimension)
28
TIME values

Numeric value can be an integer or
a floating point number.
Numeric value is optional. If not given, 1 is
implied.
Numeric value and dimension MUST be
separated by a space.

29
Units of time

Unit Definition
Base Unit
fs femtoseconds (10-15 seconds)
Derived Units
ps picoseconds (10-12 seconds)
ns nanoseconds (10-9 seconds)
us microseconds (10-6 seconds)
ms miliseconds (10-3 seconds)
sec seconds
min minutes (60 seconds)
hr hours (3600 seconds)

30
Values of the type TIME

Value of a physical literal is defined in terms
of integral multiples of the base unit, e.g.
10.65 us 10,650,000,000 fs
10.65 fs 10 fs
Smallest available resolution in VHDL is 1 fs.
Smallest available resolution in simulation can
be
set using a simulator command or parameter.

31
Arithmetic operations on values of the type TIME

Examples
7 ns 10 ns 17 ns
1.2 ns 12.6 ps 1187400 fs
5 ns 4.3 21.5 ns
20 ns / 5ns 4

32
Records
33
Records Examples (1)

type opcodes is (add, sub, and, or)
type reg_number is range 0 to 8
type instruction is record
opcode opcodes
source_reg1 reg_number
source_reg2 reg_number
dest_reg reg_number
displacement integer
end record instruction

34
Records Examples (2)

type word is record
instr instruction
data bit_vector(31 downto 0)
end record instruction
constant add_instr_1_3 instruction
(opcode gt add,
source_reg1 dest_reg gt 1,
source_reg2 gt 3,
displacement gt 0)

35
Asserts
36
Assert

Assert is a non-synthesizable statement
whose purpose is to write out messages
on the screen when problems are found
during simulation.
Depending on the severity of the problem,
The simulator is instructed to continue
simulation or halt.

37
Assert - syntax

ASSERT condition
REPORT message
SEVERITY severity_level
The message is written when the condition
is FALSE.
Severity_level can be
Note, Warning, Error (default), or Failure.

38
Assert - Examples

assert initial_value lt max_value
report "initial value too large"
severity error
assert packet_length / 0
report "empty network packet received"
severity warning
assert false
report "Initialization complete"
severity note

39
Variables
40
Variable Example (1)

LIBRARY ieee
USE ieee.std_logic_1164.all
ENTITY Numbits IS
PORT ( X IN STD_LOGIC_VECTOR(1 TO 3)
Count OUT INTEGER RANGE 0 TO 3)
END Numbits

41
Variable Example (2)

ARCHITECTURE Behavior OF Numbits IS
BEGIN
PROCESS(X) count the number of bits in X equal
to 1
VARIABLE Tmp INTEGER
BEGIN
Tmp 0
FOR i IN 1 TO 3 LOOP
IF X(i) 1 THEN
Tmp Tmp 1
END IF
END LOOP
Count lt Tmp
END PROCESS
END Behavior

42
Variables - features

Can only be declared within processes and
subprograms (functions procedures)
Initial value can be explicitly specified in the
declaration
When assigned take an assigned value immediately
Variable assignments represent the desired
behavior, not the structure of the circuit
Should be avoided, or at least used with caution
in a synthesizable code

43
Advanced Testbenches
44
Using Arrays of Test Vectors In Testbenches
45
Testbench (1)