Frequency Synthesizer Design

1
3.1-10.3GHz, 11 bands, OFDM UltraWideBand Receiver
Alberto
Valdes-Garcia, Chinmaya Mishra, Fan Xiaohua,
Faramarz Bahmani, Lin Chen. José Silva-Martinez,
Edgar Sánchez-Sinencio
Department of Electrical Engineering Analog
Mixed-Signal Center Texas AM University
http//amsc.tamu.edu/amscmain.html
2
Presentation Outline

• Introduction
• Previous Experience in Receiver Implementations
• Overview of Short Range Wireless Communications
• Overview of UltraWideBand (UWB) Technology
• 3.1 10.3 GHz Multi Band UWB Receiver
• Implementation Challenges
• Proposed UWB Receiver Architecture
• RF Front-End
• Frequency Planning and Synthesizer Architectures
• 1Gs/s time-interleaved ADC
• Baseband Blocks Linear Phase LPF and VGA
• Summary

3
0.35mm CMOS Bluetooth Receiver IC

• Low-IF architecture with GFSK demodulator
• Developed in 2000 and 2001 by 7 Ph.D. students

4
0.35mm CMOS Bluetooth Low-IF Receiver IC

• Publications
• Wenjun Sheng, Bo Xia, Emira, A., Chunyu Xin,
  Valero-Lopez, A.Y., Sung Tae Moon,
  Sanchez-Sinencio, E., A 3 V, 0.35 µm CMOS
  Bluetooth receiver IC, IEEE Radio Frequency
  Integrated Circuits (RFIC) Symposium, 2002 , pp.
  107110. Best Student Paper Award - Third Place
• Wenjun Sheng, Bo Xia, Emira, A., Chunyu Xin, Sung
  Tae Moon, Valero-Lopez, A.Y., Sanchez-Sinencio,
  E., A monolithic CMOS low-IF bluetooth receiver,
  Proceedings of the IEEE Custom Integrated
  Circuits Conference , 2002, pp. 247 250
• A.A. Emira and E. Sánchez-Sinencio, A Pseudo
  Differential Complex Filter for Bluetooth With
  Frequency Tuning, IEEE Transactions on Circuits
  and Systems II, Vol. 50, No. 10, pp. 742-754,
  October 2003.
• Bo Xia Chunyu Xin Wenjun Sheng Valero-Lopez,
  A.Y. Sanchez-Sinencio,E.,"A GFSK Demodulator for
  Low-IF Bluetooth Receiver", IEEE Journal of
  Solid-State Circuits, Vol. 38 No. 8, August 2003,
  pp. 1405-1410
• Wenjun Sheng, Bo Xia, Emira, A.E., Chunyu Xin,
  Valero-Lopez, A.Y., Sung Tae Moon,
  Sanchez-Sinencio, E., "A 3-V, 0.35um CMOS
  Bluetooth receiver IC", IEEE Journal of
  Solid-State Circuits , Vol. 38 No. 1 , Jan 2003,
  pp. 30 -42

5
0.25mm BiCMOS Dual Mode Bluetooth/Wi-Fi Receiver

• Developed between spring of 2002 and summer of
  2003 by a team of 7 Ph.D. students.

6
0.25mm BiCMOS Dual Mode Bluetooth/Wi-Fi Receiver

• Single direct-conversion architecture for both
  standards
• Shared RF Front-End and programmable baseband
  blocks

7
0.25mm BiCMOS Dual Mode Bluetooth/Wi-Fi Receiver

• Publications
• A. Emira, A. Valdes-Garcia, B. Xia, A. N.
  Mohieldin, A. Y. Valero-Lopez, S. T. Moon, C,
  Xin, and Sanchez-Sinencio,E. "A Dual Mode
  802.11b/Bluetooth Receiver in 0.25um BiCMOS",
  IEEE International Solid-State Circuits
  conference, pp. 153-154 San Franciso, February ,
  2004.
• A. Emira, A. Valdes-Garcia, B. Xia, A. N.
  Mohieldin, A. Y. Valero-Lopez, S. T. Moon, C,
  Xin, and Sanchez-Sinencio,E. "A Dual Mode
  Direct-Conversion Bluetooth/802.11b Receiver",
  Radio Frequency Integrated Circuits (RFIC)
  Symposium, 2004 IEEE , June 2004.
• B. Xia, A. Valdes-Garcia, E. Sánchez-Sinencio, "A
  configurable time-interleaved pipeline ADC for
  multi-standard wireless receivers", European
  Solid-State Circuits Conference, Belgium, Sep,
  2004.
• A. N. Mohieldin, E. Sánchez-Sinencio, " A
  Dual-mode Low-Pass Filter for 802.11b/bluetooth
  Receiver" European Solid-State Circuits
  Conference, Belgium, Sep, 2004.

8
Wireless Standards
9
Short-Range Wireless Communications
10
Presentation Outline

• Introduction
• Previous Experience in Receiver Implementation
• Overview of Short Range Wireless Communications
• Overview of UltraWideBand (UWB) Technology
• 3.1 10.3 GHz Multi Band UWB Receiver
• Implementation Challenges
• Proposed UWB Receiver Architecture
• Frequency Planning and Synthesizer Architectures
• RF Front-End
• 1Gs/s time-interleaved ADC
• Summary

11
UWB Technology Motivation

• Growing demand for wireless data capability in
  electronic devices at higher data rates and at
  lower cost and power.
• Crowding in radio spectra that regulatory
  authorities segment and license in traditional
  ways.
• Growth of high-speed wired access to the Internet
  in enterprises, homes and public spaces.

How to achieve high data rates (gt100Mbps) in
short-range wireless communications?
12
Shannon-Hartley channel capacity theorem

• C Maximum channel capacity in bits/sec
• PS Average signal power at the receiver
• N0 Noise power per unit Hz
• BW Channel bandwidth

• Channel capacity increases linearly with
  bandwidth but only logarithmically with
  signal-to-noise ratio (SNR).
• High data rates can be achieved with a low RF
  transmit power by using a larger bandwidth.

13
UWB Technology FCC regulations (April 2002)

• Frequency range 3.1 to 10.6GHz
• Minimum allowed bandwidth 500MHz
• Transmit power -41dBm/MHz
• Below unintentional radiation limits.
• No interference to other communication devices.

14
UWB Applications
High data rates ( 100 480 Mbps ) in short
distances ( lt 10m ) .
Wireless Transfer of Information from Anywhere at
Anytime
15
UWB Technology The IEEE 802.15 standard

• Currently under development by the IEEE working
  group on high data rate WPAN.
• Two competing proposals
• Direct sequence CDMA (Code Division Multiple
  Access) spread the data transmission over the
  entire bandwidth.
• Multiband OFDM (Orthogonal Frequency Division
  Multiplexing) split the available bandwidth in
  528MHz bands
• The Multiband OFDM proposal has the strongest
  support from the semiconductor and consumer
  applications industry and is the approach
  followed on this project.

16
Presentation Outline

• Introduction
• Overview of Short Range Wireless Communications
• Previous Experience in Receiver Implementation
• Overview of UltraWideBand (UWB) Technology
• 3.1 10.3 GHz Multi Band UWB Receiver
• Implementation Challenges
• Proposed UWB Receiver Architecture
• RF Front-End
• Frequency Planning and Synthesizer Architectures
• 1Gs/s time-interleaved ADC
• Baseband Blocks Linear Phase LPF and VGA
• Summary

17
Multiband OFDM UWB ReceiverImplementation
Challenges

• In the last decade, the research on circuits for
  wireless communications has focused on
  implementations for narrow-band systems such as
  Bluetooth and 802.11a/b/g.
• Only the band between 3-5GHz has been considered
  for the commercial UWB products to be deployed in
  the near (2-3 years) future.
• This research addresses the implementation of a
  multi-band UWB receiver for the entire frequency
  range approved by the FCC.

18
Main Project Goals

• Develop an efficient multi-band UWB receiver
  architecture for the entire 3.1-10.3 GHz band.
• Design of a 3.1-10.3GHz RF front-end with an
  in-band notch in the receive path (to suppress
  the U-NII band interferers in the 5 to 6 GHz
  band) and broadband matching in a commercial IC
  package.
• Design of a frequency synthesizer to efficiently
  generate 11 frequencies in the range of 3.1 to
  10.3 GHz with switching times of less than 5ns
  between adjacent bands.
• Design of a low power 6bit 1Gs/s ADC.
• At the system level, the full integration from
  the RF front-end to the ADC will be tackled,
  optimizing the circuit specifications to attain a
  low power implementation.
• The receiver is being implemented using BiCMOS
  0.25um process.

19
Proposed UWB Receiver Architecture

• Direct Conversion Receiver.
• Full implementation from LNA to ADC.
• On-Chip Synthesizer generates the 11 required
  carriers.

20
Preliminary Power Distribution

• Power for baseband blocks is for I and Q channels
• ADC and VGA are implemented with CMOS devices

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Project Schedule
  2004 2004 2004 2004 2004 2004 2005 2005 2005 2005 2005 2005
Phase Spring Spring Summer Summer Fall Fall Spring Spring Summer Summer Fall Fall
System Design                        
Circuit Design                        
Layout and Tape-out of RF blocks                        
Layout and Tape-out of Baseband blocks                        
System Integration and Tape-out                        
Characterization of RF Blocks                        
Characterization of Baseband Blocks                        
Receiver Characterization                        
Documentation                        
Up-coming Milestones Submission of theoretical
paper on UWB synthesizer architectures December
13th RF blocks IC returning from fabrication
January 25th Tape-out of IC with base-band
blocks February 14th Tape-out of receiver IC
February 14th
22
Current Status

• The receiver architecture and specifications for
  the building blocks have been defined.
• A first version of the LNA and the Frequency
  synthesizer has been sent for fabrication.
  Post-layout simulation results support the
  feasibility of the design objectives.
• The schematic-level design of the baseband blocks
  (Filter, VGA and ADC) is finished.
• Tasks in progress Front-end integration, layout
  of baseband blocks, simulation of the impact of
  implementation non-idealities on the system
  performance.

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UWB LNA Frequency Synthesizer
SYNTHESIZER
LNA
QUADRATURE VCO
24
Presentation Outline

• Introduction
• Overview of Short Range Wireless Communications
• Previous Experience in Receiver Implementation
• Overview of UltraWideBand (UWB) Technology
• 3.1 10.3 GHz Multi Band UWB Receiver
• Implementation Challenges
• Proposed UWB Receiver Architecture
• RF Front-End
• Frequency Planning and Synthesizer Architectures
• 1Gs/s time-interleaved ADC
• Baseband Blocks Linear Phase LPF and VGA
• Summary

25
System Specifications
Parameter/Block LNA Mixer VGA1 Filter VGA2
NF dB 3 15 12 36 25
Max. Gain dB 15 15 6 0 42
Min. Gain 15 15 0 0 0
IIP3 dBm -10 5 20 18 12
Adjacent Band Attenuation dB 0 0 5 15 3

• Achieved overall NF is 6.1dB and overall IIP3 is
  15dBm
• Target Sensitivity is 73dBm
• Models in MATLAB and SystemView were created to
  support the system-level design process

26
LNA Core Schematic

• Considerations to attain 3-10GHz input match in
  QFN64 package
• A differential topology is employed to prevent
  that the bonding wire becomes part of the
  degeneration inductance.
• Two pins in parallel for each input reduce the
  effective package inductance.
• A large emitter length is used.

27
Package Model
PIN
PAD

• 64 pin, Metric Quad Flat Pack (MQFP) package from
  AMKOR.
• Bonding wire of length 1mm, and bonding wire
  inductance of 1nH/mm are assumed.

28
Notch Filter with Capacitor Array

• The notch filter provides a low-impedance path at
  the collector of the input transistors (Q1) for
  the undesired frequencies (5.1-5.3GHz).
• LN and CN resonate around 5.2GHz. A negative
  resistance (Q3) improves the Q of the filter.
• A discrete bank of capacitors provides tuning to
  compensate for process variations.

29
Input Match

• S11lt-8dB in the entire band is expected.

30
LNA Voltage Gain

• Simulation for corner values of LN and CN. The
  discrete bank of capacitors is able to tune the
  filter to 5.2GHz.
• A worst-case attenuation of 11dB is expected.

31
Layout
32
LNA Performance Summary

• 1dB Bandwidth 2 10 GHz
• Gain gt15dB
• NFlt3dB
• IIP3gt-8dBm (3-6GHz), gt-4dBm (6-10GHz)
• Suppression of interferer at 5.1GHz gt10dB
• Power Consumption (without buffer)
• 5mAX2.5V 12.5mW
• Area (without buffer) 0.6mm2
• Package QFN64
• Addition of notch filter improves the overall
  dynamic range and has a negligible penalty in
  noise and power.

33
Quadrature Mixer

• A Gilbert cell is inherently broadband and
  suitable for this application.
• A quadrature mixer is chosen instead of 2
  separate mixer cells to avoid mismatch between
  the RF transistors.

34
Noise Figure and Conversion Gain
LO amplitude 100mV
35
IIP3
LO amplitude 100mV
36
Mixer Performance Summary

• Conversion Gain 14dB
• NF 16dB
• IIP3 1dBm (3GHz), -0.5dBm (10GHz)
• Power Consumption 2mAX2.5V 5mW
• Main remaining design issues
• Mixer-Filter interface implementation
• Design of a broadband buffer to couple the
  synthesizer and the LO port.

37
Presentation Outline

• Introduction
• Overview of Short Range Wireless Communications
• Previous Experience in Receiver Implementation
• Overview of UltraWideBand (UWB) Technology
• 3.1 10.3 GHz Multi Band UWB Receiver
• Implementation Challenges
• Proposed UWB Receiver Architecture
• RF Front-End
• Frequency Planning and Synthesizer Architectures
• 1Gs/s time-interleaved ADC
• Baseband Blocks Linear Phase LPF and VGA
• Summary

38
Current Frequency Plan for OFDM UWB

• Entire spectrum divided in band groups of 2-3
  bands.
• 14 bands within the 3.1 10.6 GHz unlicensed
  spectrum.
• In each band group only one reference tone needs
  to be generated to generate the other bands.
• The U-NII band (5.15 5.825GHz) is also
  included.

39
Proposed Frequency Plan for OFDM UWB

• Entire spectrum divided in band groups of 2-3
  bands.
• 11 usable bands within the 3.1 10.6 GHz
  unlicensed spectrum.
• The U-NII band (5.15 5.825GHz) is completely
  avoided.

40
Logic Governing the Frequency Band Plan

• 8448MHz and 4224MHz are the two reference tones
  which are directly generated within the division
  loop.

41
Frequency Synthesis
Band fc (MHz) Frequency Synthesis
1 3696 fo/2 fo/16
2 4224 fo/2
3 4752 fo/2 fo/16
4 6336 fo - fo/8 - fo/16 - fo/16
5 6864 fo - fo/8 - fo/16
6 7392 fo - fo/8 - fo/16 fo/16
7 7920 fo - fo/16
8 8448 fo
9 8976 fo fo/16
10 9504 fo fo/8 fo/16 - fo/16
11 10032 fo fo/8 fo/16
fo 8448 MHz

• Reference tones are italicized.

42
Synthesizer Architecture with I/Q generation
scheme

• All mixers are single side-band mixers except the
  first mixer.
• All 11 frequencies are generated in both I and Q
  phase.
• The quadrature VCO operates at 8.448GHz.

43
Divide-by-2 Circuit

• Two current mode logic based flip-flops connected
  back to back form a divide-by-2 circuit.
• Buffers between dividers consist of emitter
  followers.
• Capacitors can be connected at the output nodes
  to provide filtering of harmonics.

44
Single Side-Band Mixer
Conceptual Diagram
45
Circuit to generate I and Q signals

• RC-CR network is used to generate quadrature
  signals when the 3-dB frequency of the RC and CR
  structure is at the input signal frequency.
• Varactor tuning is employed to overcome process
  variations.

46
Multiplexer and Output Buffer

• Multiplexer uses multiple differential pairs with
  a common resistive load.
• Cascode transistors improves isolation during the
  off state of a differential pair.
• Open collector configuration is used for the
  buffer to drive the package and the load of the
  instrument.

47
Output of the Frequency Synthesizer (Simulation
Results)
48
Switching between adjacent bands (Simulation
Results)

• Switching time is very small because it is mainly
  the switching of the multiplexer.

49
Layout of the Synthesizer
1.9 mm
O/P Buffer
SSB
IQ Generator
41 MUX
SSB
SSB
2.2 mm
Dummy
DSB
Divider Chain
50
Frequency Synthesizer Implementations Comparison
Table
Architecture Frequencies (GHz) Power (mW) Technology
1 3.25 6.75 (8 Bands) 95 0.13µm CMOS
2 4, 5, 6 and 7 120 0.25µm CMOS
3 3.4 - 4.5 (3 Bands) 73 0.25µm BiCMOS
4 3 8 (7 Bands) 48 0.18µm CMOS
5 3.4 - 4.5 (3 Bands) 18 0.18µm CMOS
This Work 3.7GHz 10GHz (11 bands in quadrature) 170 (including O/P Buffers, w/o VCO and PLL components) 0.25µm BiCMOS

• 1 uses 2 VCOs _at_ 8GHz and 12GHz and uses 4
  external LO frequencies for the SSB mixers.
• 2 uses 4 VCOs in a multi-mixer PLL arrangement.
• 3 uses 2 PLLs and a SSB mixer.
• 4 uses one SSB mixer to switch among 7 bands
  distributed from 3 to 8 GHz.
• 1 Sander, C. Wiesbauer, A., A 3GHz to 7GHz
  fast-hopping frequency synthesizer for UWB, 2004
  International Workshop on Ultra Wideband Systems.
  Joint with
• Conference on Ultra wideband Systems and
  Technologies, Joint UWBST IWUWBS., 18-21 May,
  2004.
• 2 Medi, A., Namgoong, W., A fully integrated
  multi-output CMOS frequency synthesizer for
  channelized receivers, Proceedings of 2003 IEEE
  System on chip (SOC)
• Conference, 17-20, Sept. 2003.
• 3 Leenaerts, D. etal., A SiGe BiCMOS 1ns fast
  hopping frequency synthesizer for UWB radio, in
  ISSCC 2005.
• 4 Lee, J., A 7-band 3 to 8GHz frequency
  synthesizer with 1ns band-switching time in
  0.18um CMOS technology, in ISSCC 2005.
• 5 Lin, C-C., A semi-dynamic regenerative
  frequency divider for mode-1 MB-OFDM UWB hopping
  carrier generation, in ISSCC 2005.

51
Possible Future Implementation

• Wideband VCO with coarse and fine tuning and
  suitable performance over the entire range
  (7.5GHz) is a significant challenge.
• Prescaler architecture might be complex to
  generate a 528MHz tone for all reference
  frequencies while maintaining the loop under lock
  conditions.
• Design would require better technology with
  reliable foundry models.

52
Presentation Outline

• Introduction
• Overview of Short Range Wireless Communications
• Previous Experience in Receiver Implementation
• Overview of UltraWideBand (UWB) Technology
• 3.1 10.3 GHz Multi Band UWB Receiver
• Implementation Challenges
• Proposed UWB Receiver Architecture
• RF Front-End
• Frequency Planning and Synthesizer Architectures
• 1Gs/s time-interleaved ADC
• Baseband Blocks Linear Phase LPF and VGA
• Summary

53
Flash ADC
N bit resolution flash ADC?Large
number of preamp 2N?Large number of comparator
2N?Large power consumption
Reducing the power consumption is the
main consideration
54
Time-interleaved SAR ADC (6-b 1G Sample/s)
Structure
Clock
?Lower power consumption43 preamps and
comparators are used
55
Proposed successive approximation ADC
S/H
?Lower power consumptionOnly 3 preamps and
comparators are used
?Speed reduces 3 times.
56
Other reference generation structure
Resistor ladder
Intermeshed resistor ladder
FasterSuitable layout for SAR
64
57
Time interleaved flash architecture
P_ADC(1G sample/s)gt2 P_ADC(500M sample/s)gt
4P_ADC(250M sample/s)
Sampling frequency Power Area Preamp and comparator number
1G P A 64
2500MHz ltP 2A 264
4250MHz ltP 4A 464
Table I
Time interleaved SAR architecture
Sampling frequency Power Area Preamp and comparator number
4250MHz P/4 A/44Digital 12
Table II
58
High speed boosted reference switch
?Pre-charge the switch ?Constant
on-resistance ?Faster switching time?period
refresh
59
Time interleaved SAR architecture design issues
Branch offset mismatch
Digital offset cancellation
One more branch is added so that the offset of
each branch is measured digitally and subtracted
from the output digital code of branch channel
Branch gain mismatch
1. S/H gain mismatch
Randomization technique
2. DAC mismatch
Share the reference resistor ladder
Clock jitter
Low jitter on chip PLL in system is used
Clock skew
Good multiphase clock generation circuits and
good layout is needed to minimize the clock skew
of different channel
60
Output spectrum of ADC (simulation results)
1 SAR 6bit ADC Branch 250MS/s
61
6bit, 1Gs/s ADC Summary

• A new successive approximation ADC architecture
• The power saving due to the combination of the
  SAR ADC and time-interleaved architecture for
  1Gsample/s 6bit ADC.
• Constant on-resistance boosted switch is used in
  the design.
• Other design issues
• 1. Digital circuit speed
• 2. Layout
• 3. Clock generation
• We are now working to solve the problem
• and finish the design

62
Presentation Outline

• Introduction
• Overview of Short Range Wireless Communications
• Previous Experience in Receiver Implementation
• Overview of UltraWideBand (UWB) Technology
• 3.1 10.3 GHz Multi Band UWB Receiver
• Implementation Challenges
• Proposed UWB Receiver Architecture
• RF Front-End
• Frequency Planning and Synthesizer Architectures
• 1Gs/s time-interleaved ADC
• Baseband Blocks Linear Phase LPF and VGA
• Summary

63
250MHz Linear Phase Biquad Filter
64
Proposed OTA
Complete schematic of the OTA with CMFB circuit
65
Summary of results for baseband filter
Input Referred Noise530uV Adjacent channel
attenuation 15dB In-band group delay variations
lt 250ns Power Consumption25mW
66
42dB, BWgt350MHz, Variable Gain Amplifier
67
VGA Simulation Results
Post Layout (Area 0.01mm2)
Gain Range GainMAX 38dB
Gain Range GainMIN 0dB
Gain Range Gain Step 2dB
f-1dB f-1dB gt350MHz
Power Buffer 9.7mW
Power No Buffer 8.7mw
IIP3_at_ GainMIN IIP3_at_ GainMIN 12.8dBm
IIP3_at_ GainMIN IIP3_at_ GainMIN -12dBm
Group Delay Variation Group Delay Variation lt80pS
68
Presentation Summary

• A Multi-band OFDM UWB receiver design for the
  entire range licensed by the FCC and data rate
  capabilities up to 480Mbps is proposed.
• The goal is to attain a fully integrated (LNA to
  ADC) 0.25um BiCMOS implementation in a commercial
  package while optimizing power consumption.
• Key building blocks include a wide band front-end
  with in-band interference rejection, 11 bands
  frequency synthesizer with band-switching time lt
  2ns and a time-interleaved 1Gs/s ADC.
• Experimental results for RF blocks are expected
  on 03/05 and receiver characterization on 08/05.