Mask Cost Reduction with Circuit Performance Consideration for Self-Aligned Double Patterning

1
Mask Cost Reduction with Circuit Performance
Consideration for Self-Aligned Double Patterning

• H. Zhang, Y. Du, M. D.F. Wong and K. Chao
• Dept. of ECE, University of Illinois at
  Urbana-Campaign

ASPDAC 2011
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Outline

• Introduction
• Overview of Self-Aligned Double Patterning (SADP)
• Problem Formulation
• Polygon Simplification Algorithm
• Experimental Results
• Conclusion

3
Introduction

• Double patterning lithography (DPL) is the
  enabling technology for printing in sub-32nm
  nodes
• DPL technologies can be classified into two major
  types
• Double-exposure double-patterning (DEDP)
• Single-exposure double-patterning (SEDP)

4
Introduction
5
Introduction

• The leading candidate among SEDP technologies is
  self-aligned double patterning (SADP)
• In SADP, since all critical features come from a
  single exposure, basically no overlay error
  exists
• SADP is an excellent option for the 1-D on-track
  design, such as memory array

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Introduction

• SADP
• Print dense lines
• The portions not on the design will be trimmed
  away by a cut mask
• However, due to the high complexity of cut mask,
  the SADP technology becomes very costly

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Overview of SADP

• SADP has two major steps
• Step 1 is dense line generation
• Suppose the intended pitch of circuit patterns is
  p
• 1-D tracks, called spacer, are first manufactured
  on the wafer with 2p pitch
• Sidewalls are deposited along the boundary of the
  spacers
• After the spacers are etched, the dense lines are
  generated by the remaining sidewalls

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Overview of SADP

• In step 2, by printing the cut patterns onto the
  features, an etching process is applied
• The features under the exposed region will be
  etched away
• The cut mask will affect the final wafer only
  where the cut is performed

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Problem Formulation

• In SADP, what the designer can control is the
  circuit wires and the corresponding cut mask
  patterns
• The more the cut can be merged together, the
  lower the edge number of the cut polygon and
  therefore the lower the cut mask cost can be
  obtained
• Extend some line-ends and reduce the edge number
  of the intended cut

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Problem Formulation
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Problem Formulation

• However, the extra wire patterns on the line-end
  will have a potential impact on the circuit
  performance
• Find an optimal way to reach the cost reduction
  target and minimize the impact on circuit
  performance simultaneously

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Problem Formulation

• Assume the track is horizontal and reduce the
  edge number of the polygon by pushing vertical
  edge inwards
• Recast the SADP cost reduction problem as a
  polygon simplification problem
• For a polygon set R r1,r2rn and a target
  edge number k
• By only pushing edges in R inwards, find a
  modified polygon set R r1,r2rn which has
  exact k total edges and minimum area change

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Polygon Simplification Algorithm

• The constrained shortest path (CSP) problem is to
  find, given an integer k, directed graph G,
  source node S and target node T, the shortest
  path from S to T that has exactly k edges in G
• CSP was initially introduced in 24 and can be
  optimally solved using dynamic programming

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Polygon Simplification Algorithm

• How to transform a polygon into a directed graph
  for CSP

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Polygon Simplification Algorithm

• Edge cost W(i,j) can be expressed by the area
  change in the following equation
• xi x location of edge i
• xmax(i,j) the inner-most position among all the
  vertical edges between hi and hj
• Lk the length of the kth vertical edge

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Polygon Simplification Algorithm
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Polygon Simplification Algorithm
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Polygon Simplification Algorithm
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Experimental Results
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Experimental Results
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Experimental Results
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Experimental Results
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Conclusion

• When the conventional DPL (DEDP) has difficulties
  handling overlay errors, SADP is considered to be
  a promising method to overcome the lithography
  challenges
• This paper present a mask cost reduction method
  with circuit performance consideration for SADP