Embedded Systems

1
Embedded Systems

• University of Belgrade
• School of Electrical Engineering
• Department of Computer Science

Authors Gvozden Marinkovic mgvozden_at_eunet.yu Niko
la Milanovic nikola99_at_eunet.yu Goran Timotic
gogi_at_beotel.yu Ivan Sokic sokic_at_eunet.yu Prof.
Dr. Veljko Milutinovic vm_at_etf.bg.ac.yu
2
Introduction

• Design
• Components
• Microcontrollers
• Communication
• Examples
• ARMs
• PIC MCUs

3
Design

• Specification
• Circuit Design
• Printed Circuit Board Layout
• Firmware
• Pilot Run
• Production

Source
AirBorn Electronics
4
Electronic Design Flowchart
Source
AirBorn Electronics
5
Specification

• Starts as collection of ideas that describe a
  device or product
• Specifications go through two phases
• first phase they describe the product as desired
  must-have, bells and whistles features
• second phase they describe the product as
  requireddescribes the product as it is required
  to be produced

Source
AirBorn Electronics
6
Specifying New Design

• Give your project a name
• Keep project name short, it saves time
• Describe your project (Opening Statement)
• Keep the first description short
• First sentence should summarize the whole
  function of the project
• Describe or name equipment, devices or interfaces
• Describe your projects market
• Describe the market need your product fulfills
• Estimate the production volume

Source
AirBorn Electronics
7
SpecificationTechnical Ingredients

• A Specification reads like a list of project
  features,describing the unit, and will usually
  include

Inputs Controls Outputs Indicators Functions
Modes of operation
Power Supply Communications Protection Fail safes
andreplaceable parts Connector types Physical
format and size
Source
AirBorn Electronics
8
Circuit Design
Part 1

• Maps out the electronics and connectionsin the
  most readily readable form
• The designer needs to do background work
• research specifications of components
• research interaction between components(especiall
  y timing and loading)
• research physical packages
• research arrangement of connector pinouts
• The finished circuit diagram is the main document
  for the design

Source
AirBorn Electronics
9
Circuit Design
Part 2

• Circuit diagram is a strict document
• A circuit diagram must reflect the actual
  constructionof the printed circuit board which
  is made from it
• Printed circuit board CAD and Schematic CADare
  tied together through a Net-check
• The circuit diagram references each part on the
  PCBwith a designator and pin numbers for each
  connection

Source
AirBorn Electronics
10
Printed Circuit Board Layout

• Connections on the PCBshould be identical tothe
  circuit diagram
• Circuit diagram is arrangedto be readable
• PCB layout is arrangedto be functional
• PCB layout can be performed
• manually (using CAD)
• in combination withan Autorouter

Source
AirBorn Electronics
11
Methods of PCB construction
Part 1

• Conventional
• Rigid PCB of thickness 1.6mm
• Wire-leaded componentsmounted on only one
  sideof the PCB
• All the leads through holes, soldered and
  clipped.
• Easier to debug and repair than Surface mount

Source
AirBorn Electronics
12
Methods of PCB construction
Part 2

• Surface Mount Technology (SMT) devices (SMD)
• PCB with tag-leaded componentssoldered flush to
  PCB pads
• Holes are still needed on the PCB, not where the
  component leads are attached
• Generally smaller than conventional
• Generally more suited to automated assembly than
  conventional

Source
AirBorn Electronics
13
Methods of PCB construction
Part 3

• Surface mount and conventional mix
• Most boards are a mix ofsurface mount
  andconventional components
• Disadvantages becausethe two technologies
  require different methods ofinsertion and
  soldering

Source
AirBorn Electronics
14
Methods of PCB construction
Part 4

• Double sided Laminate
• Tracks on both sides, normally with PTH
  holesconnecting circuitry on the two sides
  together
• Double sided component Assembly
• Mounting components on both sides of the PCB
• Normally only surface mount circuitrywould be
  mounted on both sides of a PCB

Source
AirBorn Electronics
15
Methods of PCB construction
Part 5

• Multi-layer
• PCB Laminate manufacturedwith more than two
  layers of copper tracks,by using a sandwich
  construction
• Cost of the laminate reflects the number of
  layers
• Used to
• route complicated circuitry
• distribute the power supplymore effectively

Source
AirBorn Electronics
16
Methods of PCB construction
Part 6

• Gold plated
• Certain areas on a PCB may be gold plated for use
  as contact pads
• Flexible PCB
• Technique used extensively with
• membrane keyboards
• combination connector/circuit boards
• circuit boards to fit in awkward shapes

Source
AirBorn Electronics
17
Methods of PCB construction
Part 7

• Chip On Board (COB)
• IC is attached direct to a PCB
• Bond out wires from the IC connect directly to
  PCB lands
• Chip is covered with a black blob of epoxy
• Used mostly with very high volume, cost sensitive
  applications

Source
AirBorn Electronics
18
Methods of PCB construction
Part 8

• Phenolic PCB
• Phenolic is a cheaper PCB laminate material
• Daughterboard
• Circuit board mounted to another circuit board

Source
AirBorn Electronics
19
Printed Circuit Board Etching
Part 1

• CAD File processing
• PCB CAD files are sent tothe PCB Manufacturer
• PCB manufacturer inspects the files, making a
  drill list and adding identification
• CAD files are processed andsent to a
  photoplotterto turn into film artwork

Source
AirBorn Electronics
20
Printed Circuit Board Etching
Part 2

• Laminate drilling and electroplating
• Laminates are drilled with holes
• Drilled laminates are coatedin a chemical to
  enhance electroplating of holes
• Laminates are put ina copper plating bath,all
  the holes are electroplated
• This connects pads on opposite sides of the PCB,
  electrically

Source
AirBorn Electronics
21
Printed Circuit Board Etching
Part 3

• Laminate etching
• The laminates are coated with a UV-sensitive
  photo-resist
• The track pattern is imaged onto each side of
  each PCB,using the photoplots and UV light
• The photo-resist is developed,leaving
  photo-resist only where copper is required
• The laminates are put in acid,to etch away
  unrequired copper, forming the track pattern
• The bare copper PCB, with tracks and pads now
  finished,is cleaned

Source
AirBorn Electronics
22
Printed Circuit Board Etching
Part 4

• Laminate solder masking and tinning
• The bare copper PCB is silkscreened with a solder
  mask (usually green)
• The solder mask is dried or cured
• The PCB is tinned - solder is applied to exposed
  pads
• The PCB is levelled - bumps in the solder is made
  flat by using hot air or hot oil

Source
AirBorn Electronics
23
Printed Circuit Board Etching
Part 5

• Final stages
• The PCB is silkscreened with component
  identification lettering (usually white)
• The silkscreen legendis dried or cured
• Any final drilling is done of holes that are not
  to be plated through, any routing is done, and
  the laminate is cut into individual printed
  circuit boards

Source
AirBorn Electronics
24
PCB Assembly

• Assemblies should be
• maintainable
• repairable
• durable and
• easy to install

Source
AirBorn Electronics
25
PCB Documentation
Part 1

• Front Cover
• Title, date, version number, customer details,
  project features
• Schematic
• ECO Sheet
• Details of any circuit modifications
• Bill of material
• The parts list
• Parts key
• A glossary of the part number abbreviations, with
  package sizes,lead spacing, tolerance notes and
  preferred types

Source
AirBorn Electronics
26
PCB Documentation
Part 2

• Front panel artwork
• Manufacturing notes
• Contains the notes relating to previous
  production runs- for instance problems
  encountered, methods of testing
• Drilling diagram
• Showing the positioning and size of every hole on
  the PCB
• Actual size PCB overlay
• Showing the positioning and identification of the
  PCB components
• The plan is printed actual size to allow
  components to be placed against it to check for
  fit

Source
AirBorn Electronics
27
Firmware

• The major steps in Firmware design are
• Program Specification
• Program Design
• Writing code
• Program Test

Source
AirBorn Electronics
28
Program Specification

• The specification for the Electronic Product
  being designedwill usually also be the
  specification for the programming required
• The program specification will required the
  writer to go into substantial detail about how
  the product actually operates,and how it is used
• A thorough program specification leads straight
  in toFlow charts and timing diagrams,which are
  components of Program Design

Source
AirBorn Electronics
29
Program Design

• The program design stage lays out the structure
  andalgorithms of the firmware
• The structure and algorithms may be laid out as
• flowchart
• timing diagram
• description of a protocol
• memory map or
• equation

Source
AirBorn Electronics
30
Writing Code

• If the program is well specified andthe
  algorithm design stage has been thorough,the
  actual code writing stage can become almost
  mechanical
• By defining the software at the outset, before
  code is written,a much more defined, integrated,
  set of code can be produced
• The extra space occupied by comments costs
  nothing,and if the comments are well laid
  outthere is no possibility that they can
  detractfrom understanding the code

Source
AirBorn Electronics
31
Program Test

• Divide the testing of the design into small,
  autonomous units
• It is easier to detect faultsbefore they are
  compounded by other factors
• Program testing requires getting diagnostic data
  out of the target, for analysis
• By emulation tools,or through the hardware
  itself (for instance a serial port)

Source
AirBorn Electronics
32
Pilot Run

• To test the product further, a Pilot run
  normally follows the prototyping stage
• Small quantity of units are field trialed in a
  beta test
• Opportunity to assess the manufacturability of
  the design,and the usability of the
  documentation

Source
AirBorn Electronics
33
Production

• Following the pilot run there will likely be
  changesto the firmware, and possibly the circuit
  design,as the unit develops into a stable, final
  product
• This process is controlled by ECOs and version
  numbers
• The cost, style of design of the final
  production, is heavily influenced by the number
  of units manufactured

Source
AirBorn Electronics
34
Components

• Capacitors
• Resistors
• Transistors
• Diodes
• Oscillators and Crystals
• AD Converters
• DA Converters
• LCD (Liquid Crystal Display)
• Operational Amplifier
• Sensors and Transducers

35
Oscillators and Crystals

• Feedback Oscillators
• Loop Gain
• How Feedback Oscillators Work?
• Quartz Crystal
• Crystal Parameters
• Equivalent Circuit
• Load Capacitance
• Series vs. Parallel Crystals
• Frequency Tolerance

36
AD Converters

• Converts analog input to a digital value and
  outputs it as serial or parallel data
• Basic attributes
• number of channels for analog input
• approximation type
• resolution (number of bits)
• conversion speed
• serial or parallel output
• operating temperature range
• errors (linearity, differential linearity, total)

37
DA Converters

• Converts digital input to an analog value and
  outputs it as a DC voltage
• Basic attributes
• conversion method
• output settling time
• analog output sink/source current
• operating temperature range

38
LCD (Liquid Crystal Display)

• Used in low power devices (voltage 2-3V)
• Layer of liquid crystal (10-12?m thick) is
  formed between two glass plates
• When applied, electrical field polarizes
  molecules of liquid crystal and the chosen
  segment becomes visible
• Beside low power devices, LCD is becoming a
  standard option for desktop monitors - flat panel
  TFT LCD (clearer picture with higher resolution)
• Problem viewing angle

39
Operational Amplifier

• Realization with differential amplifier (IC or
  discrete logic)
• Circuits with negative or positive feedback
  (amplifiers and oscillators)
• Basic parameters
• gain
• input and output resistance
• bandwidth (frequency characteristics)
• voltage and current drift
• max. output current

40
Sensors and Transducers

• Classification
• physical property (piezoelectric, photovoltaic,
  etc.)
• function (measurement of length, temperature,
  etc)
• Radiant, gravitational, mechanical, thermal,
  electrical, magnetic, molecular, atomic, nuclear
• The signal is fed into an input transducer, which
  changes the form of energy, usually into
  electrical.
• A modifier, usually an amplifier, and an output
  transducer then convert the energy into a form to
  be displayed or recorded.

41
Sensors and Transducers

• The following is a diagram representative of this
  system

• Three basic types of transducers are
• self generating
• modulating
• modifying

42
Microcontrollers

• Specially designed microprocessors
• It is small on chip computer
• Highly integrated chipincludes all or most parts
  needed for controller
• A typical microcontroller has
• bit manipulation
• easy and direct access to I/O
• quick and efficient interrupt processing
• Microcontroller drastically reduces design cost

43
Worldwide Microcontroller shipments- in millions
of dollars -
Source
WSTS ICE
44
Worldwide Microcontroller shipments- in millions
-
Source
WSTS ICE
45
Applications

• Appliances(microwave oven, refrigerators,
  television and VCRs, stereos)
• Computers and computer equipment(laser printers,
  modems, disk drives)
• Automobiles(engine control, diagnostics, climate
  control),
• Environmental control(greenhouse, factory, home)
• Instrumentation
• Aerospace
• Robotics, etc...

46
Flavors

• 4, 8, 16, or 32 bit microcontrollers
• specialized processors include features specific
  for
• communications,
• keyboard handling,
• signal processing,
• video processing, and other tasks.

47
Popular Microcontrollers
Part 1

• 8048 (Intel)
• 8051 (Intel and others)
• 80c196 (MCS-96)
• 80186,80188 (Intel)
• 80386 EX (Intel)
• 65C02/W65C816S/W65C134S (Western Design Center)
• MC14500 (Motorola)

48
Popular Microcontrollers
Part 2

• 68HC05 (Motorola)
• 68HC11 (Motorola and Toshiba)
• 683xx (Motorola)
• PIC (MicroChip)
• COP400 Family (National Semiconductor)
• COP800 Family (National Semiconductor)
• HPC Family (National Semiconductor)
• Project Piranha (National Semiconductor)

49
Popular Microcontrollers
Part 3

• Z8 (Zilog)
• HD64180 (Hitachi)
• TMS370 (Texas Instruments)
• 1802 (RCA)
• MuP21 (Forth chip)
• F21 (Next generation Forth chip)

50
Programming Languages
Part 1

• Machine/Assembly language
• Interpreters
• Compilers
• Fuzzy Logic and Neural Networks

51
Development Tools
Part 1

• Simulators
• Resident Debuggers
• Emulators
• Java on Embedded Systems

52
Choosing microcontoller

• Technical support
• Development tools
• Documentation
• Purchasing more devices at one manufacturer(A/D,
  memory, etc.)
• Additional features(EEPROM, FLASH, LCD driver,
  etc.)

53
Microcontrollers

• Basic parts are
• Central Processing Unit
• RAM
• EPROM/PROM/ROM or FLASH Memory
• I/O serial or/and parallel
• timers
• interrupt controller
• Optional parts are
• Watch Dog Timer
• AD Converter
• LCD driver
• etc.

54
Intel 8051

• A typical 8051 contains
• CPU with Boolean processor
• 5 or 6 interrupts2 external, 2 priority levels
• 2 or 3 16-bit timer/counters
• programmable full-duplex serial port
• 32 I/O lines (four 8-bit ports)
• RAM
• ROM/EPROM in some models

55
Intel 8051 Pin Description
Part 1

• VSS - Ground 0V
• VCC - Power Supply
• P0.0-P0.7 - Port 0
• Open drain,bi-directional I/O port
• Pins that have 1s written to them float and can
  be used as high-impedance inputs
• Multiplexed low-order address and data bus during
  accesses to external program and data memory

56
Intel 8051 Pin Description
Part 2

• P2.0-P2.7 - Port 2
• Bi-directional I/O portwith internal pull-ups
• Pins that have 1s written to them float and can
  be used as high-impedance inputs.
• Port 2 emits high-order address byte during
  accesses to external program and data memory
• P3.0-P3.7 - Port 3
• Bi-directional I/O portwith internal pull-ups
• Pins that have 1s written to them float and can
  be used as high-impedance inputs.

• Port 3 serves thespecial features
• RxD - Serial input port
• TxD - Serial output port
• INT0 - External interrupt
• INT1 - External interrupt
• T0 - Timer 0 external input
• T1 - Timer 1 external input
• WR - External data memorywrite strobe
• RD - External data memory read strobe

57
Intel 8051 Pin Description
Part 3

• RST - Reset
• A high on this pinfor two machine cycles resets
  the devices
• ALE - Address Latch Enable
• Output pulse for latchingthe low byte of
  address during an access to external memory
• PSEN - Program Store Enable
• Read strobe to external program memory

• EA - External Access Enable
• EA must be externally held low to enable device
  to fetch code from external memory locations.
• XTAL1 - Crystal 1
• Input to the inverting oscillator amplifier and
  input to internal clock generator circuits
• XTAL2 - Crystal 2
• Output from the inverting oscillator amplifier

58
Intel 8051 Pin Configurations
Part 1

• Dual In-Line Package
• Plastic Lead Chip Carrier
• Plastic Quad Flat Pack

59
Intel 8051 Pin Configurations
Part 2

• 6

• 1

• 40

• 39

• 7

PQFP

• 29

• 17

• 28

• 18

• 1 NIC

• 16 P3.4/T0

• 31 P2.7/A15

• 2 P1.0

• 17 P3.5/T1

• 32 PSEN

• 3 P1.1

• 18 P3.6/WR

• 33 ALE

• 4 P1.2

• 19 P3.4/RD

• 34 NIC

• 5 P1.3

• 20 XTAL2

• 35 EA

• 6 P1.4

• 21 XTAL1

• 36 P0.7/AD7

• 7 P1.5

• 22 VSS

• 37 P0.6/AD6

• 8 P1.6

• 23 NIC

• 38 P0.5/AD5

• 9 P1.7

• 24 P2.0/A8

• 39 P0.4/AD4

• 10 RST

• 25 P2.1/A9

• 40 P0.3/AD3

• 11 P3.0/RxD

• 26 P2.2/A10

• 41 P0.2/AD2

• 12 NIC

• 27 P2.3/A11

• 42 P0.1/AD1

• 13 P3.1/TxD

• 28 P2.4/A12

• 43 P0.0/AD0

• 14 P3.2/INT0

• 29 P2.5/A13

• 44 VCC

• 15 P3.3/INT1

• 30 P2.6/A14

60
Intel 8051 CPU
Part 1

• Primary elements are
• eight bit ALUwith associated registersA, B, PSW
  and SP
• sixteen-bitProgram Counter (PC)
• Data Pointer registers

61
Intel 8051 CPU
Part 2

• The ALU can manipulate one-bit as well as
  eight-bit data types
• This features makes the 8051 especially well
  suitedfor controller-type applications
• A total of 51 separated operationsmove and
  manipulate three data types
• Boolean (1-bit)
• Byte (8-bit)
• Address (16-bit)

62
Intel 8051 CPU
Part 3

• Instruction types
• Arithmetic Operations
• Logic Operations for Byte Variables
• Data Transfer Instructions
• Boolean Variable Manipulation
• Program Branching and Machine Control

63
Intel 8051 CPU
Part 4

• There are eleven addressing modes
• seven for data
• four for program sequence control
• Most operations allow several addressing
  modes,bringing total number of instructions to
  111,encompassing 255 of the 256 possible 8-bit
  instruction opcodes
• 8051 instruction set fares well at bothreal-time
  control and data intensive algorithms

64
Intel 8051 Memory Organization
Part 1

• Program memory is separate distinct from data
  memory
• Each memory type has a different addressing
  mechanism,different control signals, and a
  different functions
• Architecture supports several distinct
  physical address spaces functionally separated
  at the hardware level
• On - chip program memory
• On - chip data memory
• Off - chip program memory
• Off - chip data memory
• On chip special function registers

65
Intel 8051 Memory Organization
Part 2

• Program (Code) memory
• Holds the actual 8051 program that is to be run
• Limited to 64K
• may be found on-chip as ROM or EPROM
• may be stored completely off-chip inan external
  ROM or an external EPROM
• Flash RAM is also another popular method of
  storing a program
• Various combinations of these memory types may be
  used(e.g. 4 K on-chip and 64 KB off-chip)

66
Intel 8051 Memory Organization
Part 3

• External RAM
• External RAM is any random access memory which is
  found off-chip
• External RAM is slower
• To increment an Internal RAM location by 1
  requires only 1 instruction and 1 instruction
  cycle
• To increment a 1-byte value stored in External
  RAMrequires 4 instructions and 7 instruction
  cycles
• While Internal RAM is limited to 128 bytes (256
  bytes with an 8052),the 8051 supports External
  RAM up to 64K

67
Intel 8051 Memory Organization
Part 4

• On-chip memory
• Two types
• Internal RAM and
• Special Function Register (SFR) memory
• Internal RAM is on-chip so it is the fastest RAM
  available
• Internal RAM is volatile, when the 8051 is reset
  this memory is cleared
• Special Function Registers (SFRs) are areas of
  memory thatcontrol specific functionality of the
  8051 processor

68
Intel 8051 Memory Access
Part 1

• PORT 2 High byte of addressheld for the
  duration ofread or write cycle
• PORT 0 time multiplexedlow byte of address
  with data byte
• Signal ALE used to capture the address byte into
  an external latch

69
Intel 8051 Memory Access
Part 2
70
Intel 8051 Program Memory
Part 1

• Up to 64K of Program Memory
• PSEN read strobefor all external program
  fetches
• PSEN not activated forinternal program fetches
• Depending on EA pinlowest bytes can be eitherin
  the on-chip ROM or in an external ROM

71
Intel 8051 Program Memory
Part 2

• Boot address - 0x0000
• Each interrupt is assigneda fixed location in
  Program Memory
• If interrupt is not going to used,its service
  location is available asgeneral purpose Program
  Memory

72
Intel 8051 Program Memory
Part 3

• Port 0 and Port 2 are dedicatedto bus functions
  duringexternal Program Memory fetches

73
Intel 8051 Data Memory
Part 1

• Up to 64K Data Memory
• Access to Data memory useRD or WR to strobe the
  memory

74
Intel 8051 Data Memory
Part 2

• Internal Memory Addressesare one byte wide -
  128 bytes address space(256 - Intel 8052)
• Direct addressing higher then 0x7F access one
  memory space,indirect addressing higher then
  0x7F access a different memory space
• Upper 128 and SFR spaceoccupying same block of
  addresses, although they are physically
  separate entities

75
Intel 8051 Data Memory
Part 3

• The lowest 32 bytes are groupedinto 4 banks of 8
  registers
• Program instructions call outthese registers R0
  through R7
• Two bits in the PSWselects register bank
• Register instructions are shorter
• The next 16 bytes form ablock of bit-addressable
  space

76
Intel 8051 SFR
Part 1

• SFRs are accessed as if they were normal Internal
  RAM
• SFR registers exist in the address range of 80h
  through FFh
• Each SFR has an address and a name

77
Intel 8051 SFR
Part 2
78
Intel 8051 SFR
Part 3

• Accumulator (A)
• Accumulator register
• B Register (B)
• Used during multiply and divide operations
• PSW
• Contains program status information
• Stack Pointer (SP)
• Eight bits wide
• Stack may reside anywhere in on chip RAM

• The Stack Pointer is initialized on 0x07after a
  reset, and this causes stack to begin at location
  0x08
• Data Pointer(DPTR)
• Consist high byte (DPH) and low byte (DPL)
• It may be manipulated as a 16-bit register or as
  two independent 8-bit registers

79
Intel 8051 SFR
Part 4

• Ports 0 to 3 (P0, P1, P2, P4)
• Latches of Port 0 to 3, respectively
• Serial Data Buffer (SDBF)
• It is actually two separated registers receive
  and transmit buffer registers
• When data is moved to SBUF it goes to the
  transmit buffer
• When data is moved from SBUF it comes from the
  receive buffer

• Timer Registers (T1, T0)
• (TH1, TL1) (TH0, TL0)Counting Registers for
  Timer/Counter 1 and 0
• Control Registers
• IP Interrupt priority
• IE Interrupt enable
• TMOD Timer/Counter mode
• TCON Timer/Counter control
• PCON Power control

80
Intel 8051 PSW

• Auxiliary Carry flag is used for BCD operations
• Flag 0 is available to user for general purposes
• The contest of (RS1, RS2) enable working register
  banks as follows 00 - Bank 0 0x00-0x07, 01 -
  Bank 1 0x08-0x0f,10 - Bank 2 0x10-0x17, 11
  - Bank 3 0x18-0x1F

81
Intel 8051 CPU Timing

• The internal clock generator defines the
  sequence of states that make up a machine cycle
• A machine cycle consists of 6 states, numbered S1
  through S6
• Each state time lasts for two oscillator periods
• Each state is then divided into a Phase 1 and
  Phase 2 half

82
Intel 8051 Port Structures
Part 1

• Pseudo bi-directional I/O port structure
• On Port0 R2 is disabledexcept during bus
  operations(open-collector output)
• The address latch bit is updated by direct
  addressing instructions
• The value read is OR-tied function of Q1 and
  the external device
• To use a pin for input latch must be set

83
Intel 8051 Port Interfacing

• The output buffers of Ports 0, 1, 2 and 3can
  each drive 4 LS TTL inputs
• Can be driven by open-collector and open-drain
  outputs
• 0-to-1 transitions will not be fast sincethere
  is little current pulling the pin up
• Port 0 output buffers can each drive 8 LS TTL
  inputs(external bus mode)
• As port pins PORT 0 requires external pull-ups
  to be able to drive any inputs bit

84
Intel 8051 Special Peripheral Functions

• There are few special needscommon among
  control-oriented computer systems
• keeping tracks of elapsed time
• maintaining a count of signal transitions
• measuring the precise width of input pulses
• communicating with other systems
• closely monitoring asynchronous external events

85
Intel 8051 Timers/Counters
Part 1

• Two 16-bit Timer/Counter registers
• Timer Register is incremented every machine
  cycle (1 machine cycle 12 oscillator periods)
• Counter Register is incremented in response
  to1-to-0 transition at its corresponding
  external input pin (T0, T1)
• External input is sampled at S5P2 of every
  machine cycle
• When the samples show high in one cycle and low
  in the next, the count is incremented
• The new count value is appears in S3P1of the
  following detection cycle
• Max count rate is 1/24 of oscillator frequency
• TMOD - Timer/Counter mode register
• TCON - Timer/Counter control register

86
Intel 8051 Timers/Counters
Part 2

• GATE Gating control when set
• C/T Counter or Timer Selector
• M1 M0
• 00 8-bit Timer/Counter with 5-bit prescaler
• 01 16-bit Timer/Counter
• 10 8-bit auto reload Timer/Counter
• 11 (Timer0)TL0 is 8-bit Timer/Counter
  controlled by Timer0 control bitsTH0 is 8-bit
  timer only controlled by Timer1 control bits
• 11 (Timer1) Timer/Counter is stopped

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Intel 8051 Timers/Counters
Part 3

• TF Overflow flag
• Set by hardware on Timer/Counter overflow
• Cleared by hardware when processor vectors to
  interrupt routine
• TR Run control bit
• Set/Cleared by software to turn Timer/Counter
  on/off
• IE Interrupt Edge flag
• Set by hardware when external interrupt edge
  detected
• Cleared when interrupt processed
• IT Interrupt Type control bit
• Set/Cleared by software to specify falling
  edge/low level triggered external interrupts

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Intel 8051 Timers/Counters
Part 4
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Intel 8051 Timers/Counters
Part 5
90
Intel 8051 Timers/Counters
Part 6
91
Intel 8051 Timers/Counters
Part 7
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Intel 8051 Serial Port Interface
Part 1

• Full-duplex
• Serial port receive and transmit registersare
  both accessed at Special Function Register SBUF
• Writing to SBUF loads the transmit register
• Reading from SBUF accesses a physically separated
  receive register
• Four modes of operation
• In all four modes transmission is initiated
  byany instruction that uses SBUF as destination
  register
• Reception is initiated in Mode 0 by condition
  RI0 and REN1In other modes by the incoming
  start bit if REN1
• SCON - Serial Port Control Register

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Intel 8051 Serial Port Interface
Part 2

• SM0 SM1
• 00 Mode 0, Shift register, fosc//12
• 01 Mode 1, 8-bit UART, variable
• 10 Mode 2, 9-bit UART, fosc//32 or fosc//64
• 11 Mode 3, 9-bit UART, variable
• SM2 Enables multiprocessor features in Mode 2
  and Mode 3
• When the stop bit is received,the interrupt will
  be activated only if RB81 (9th bit 1)
• REN Enables serial reception
• Set/Clear by software

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Intel 8051 Serial Port Interface
Part 3

• TB8 9th data bit that will be transmitted in
  Mode2 and Mode3
• Set/Clear by software
• RB8 9th data bit that was received in Mode2 and
  Mode3In Mode 1, if SM20, is the stop bit that
  was received
• TI Transmit interrupt flag
• Set by hardware. Must be cleared by software
• RI Receive interrupt flag
• Set by hardware. Must be cleared by software

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Intel 8051 Serial Port Interface
Part 4

• MODE 0
• Serial data enters and exits through RXD
• TXD outputs shift clock
• 8 bits are transmitted/received 8 data bits (LSB
  first)
• The baud rate is fixed at 1/12 oscillator
  frequency
• MODE 1
• Serial data enters through RXD, exits through TXD
• 10 bits are transmitted/receivedstart bit(0), 8
  data bits (LSB first), stop bit(1)
• On receive the stop bit goes into RB8 in SCON
  register
• The baud rate is variable

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Intel 8051 Serial Port Interface
Part 5

• MODE 2
• Serial data enters through RXD, exits through TXD
• 11 bits are transmitted/receivedstart bit(0), 8
  data bits (LSB first), a programmable 9th bit,
  stop bit(1)
• On transmit, the 9th bit is TB8 in SCON register
• On receive, the 9th bit goes into RB8 in SCON
  register
• The baud rate is programmable to either1/32 or
  1/64 the oscillator frequency
• MODE 3
• Same as MODE 2 in all respects except baud rate
• The baud rate is variable

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Intel 8051 Serial Port Interface
Part 6

• Mode 0 Baud Rate Oscillator frequency/12
• Mode 2 Baud Rate (2SMOD)/64Oscillator
  frequency
• SMOD is bit in Special Function Register PCON
• Mode 1 and Mode3 baud rate is determined by
  Timer 1 overflow rate
• Mode 1,3 Baud Rate (2SMOD)/32 Timer 1
  Overflow Rate
• Timer mode, auto-reload Timer Overflow
  RateOscillator frequency/12(256-TH1)

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Intel 8051 Serial Port Interface
Part 7
99
Intel 8051 Interrupt Control
Part 1

• EA Enable/Disable all interrupts
• If EA0 no interrupts will be acknowledged
• If EA1 each interrupt source is individually
  enabled/disbled
• ES Serial Port interrupt enable bit
• ET Timer interrupt enabled bit
• EX External interrupt enable bit

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Intel 8051 Interrupt Control
Part 2

• 5 interrupt sources
• 2 external(INT0, INT1)
• 2 timers(TF0, TF1)
• Serial Port(RI or TI)

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Intel 8051 Interrupt Control
Part 3

• External interrupts
• Level-activated or transition-activateddepending
  on bits IT0, IT1 in register TCON
• The flags that generate these interrupts
  areIE0, IE1 in TCON
• Cleared by hardware if the interrupt was
  transition-activated
• if the interrupt was level-activated,external
  source controls request bits
• If external interrupt is level-activated, the
  external source has to hold request active,until
  the requested interrupt is actually generated.
• External source has to deactivate the
  requestbefore interrupt service is completed,or
  else another interrupt will be generated

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Intel 8051 Interrupt Control
Part 4

• Timer interrupts
• Interrupts are generated by TF0 and TF1 in
  register TCON
• When a timer interrupt is generated, the flag
  that generated it is cleared by hardware when the
  service routine is vectored to
• Serial Port interrupt
• generated by the logical OR of bits RI and TI in
  register SCON

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Intel 8051 Interrupt Control
Part 5

• Priority bit1 High Priority Priority bit0
  Low Priority
• PS Serial Port priority bit
• PT Timer priority bit
• PX External priority bit

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Intel 8051 Interrupt Control
Part 6

• A low-priority interrupt can be interrupted by a
  higher priority interrupt, but not by another
  low-priority interrupt
• A high priority interruptcannot be interrupted
  by any other interrupt source
• If two requests are received simultaneously,the
  request of higher priority level is serviced
• If requests of the same priority level are
  received simultaneously, an internal polling
  sequence determines which request is serviced
• priority within level'' structure is only
  usedto resolve simultaneous requests of the same
  priority level.

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Intel 8051 Interrupt Control
Part 7
106
Intel 8051 Interrupt Control
Part 8

• The INT0 and INT1 levels are inverted and
  latchedinto the Interrupt Flags IE0 and IE1 at
  S5P2 of every machine cycle
• Serial Port flags RI and TI are set at S5P2
• The Timer 0 and Timer 1 flags, TF0 and TF1,are
  set at S5P2 of the cycle in which the timers
  overflow
• If a request is active and conditions are
  right,a hardware subroutine call to the
  requested service routinewill be the next
  instruction to be executed
• In a single-interrupt system, the response time
  is alwaysmore than 3 cycles and less than 9
  cycles

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Intel 8051 Reset
Part 1

• The reset input is the RST pin, which has a
  Schmitt Trigger input
• Accomplished by holding the RST pin highfor at
  least two machine cycles (24 oscillator
  periods)while the oscillator is running
• The RST pin is sampled during S5P2 of every
  machine cycle
• While the RST pin is high,the port pins, ALE and
  PSEN are weakly pulled high
• Driving the ALE and PSEN pins to 0 while reset is
  activecould cause the device to go into an
  indeterminate state

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Intel 8051 Reset
Part 2
109
Intel 8051 Power On Reset

• RST pin must be held high long enough to allow
  the oscillator to start up plus two machine
  cycles
• The oscillator start-up time depend on the
  oscillator frequency
• Port pins will be in a random state until the
  oscillator has started and the internal reset
  algorithm has written 1s to them
• Powering up the device without a valid reset
  could cause the CPU to start executing
  instructions from an indeterminate location

110
Intel 8051 EPROM Versions

• Electrically programmable by user
• Relative slow
• Limited number of erase/write cycles

111
Intel 8051 OTP Versions

• One Time Programmable
• It is standard EPROM without erasing window
• It is used for limited production

112
Intel 8051 FLASH Versions

• Supports in-system and in-board code changes
• Electrically erasable
• Reduces code inventory and scrap
• Simplifies the task of upgrading code and
  reduces upgrade cycle time
• Provides just-in-time system software downloads
• Truly non-volatile

113
Intel 8051 The On-Chip Oscillator

• Intel 8051 microcontrollers have an on-chip
  oscillator
• resonators are connected between XTAL1 and XTAL2
  pins
• external oscillators (HMOS or CMOS)

114
Intel 8051 Power Management

• Low power devices
• Power saving
• Voltage monitoring

115
Intel 8051 Power Reduction Modes

• CHMOS versions provides power reduced modes of
  operations
• There are two power reducing modes Idle and Power
  Down
• In the Idle mode oscillator continues to
  ranInterrupt, Timer and Serial Port blocks
  continue to be clockedclock signal is gated off
  to the CPU
• In the Power Down mode the oscillator is frozen

116
Intel 8051 Instruction Set
Part 1
117
Intel 8051 Instruction Set
Part 2
118
Intel 8051 Instruction Set
Part 3
119
Intel 8051 Instruction Set
Part 4
120
Intel 8051 Instruction Set
Part 5
121
Intel 8051 Instruction Set
Part 6
122
Intel 8051 Instruction Set
Part 7
123
Intel 8051 Instruction Set
Part 8
124
Intel 8051 Addressing Modes

• Immediate Addressing
• Direct Addressing
• Indirect Addressing
• refers to Internal RAM, never to an SFR
• External Direct
• only two commands that use External Direct
• DPTR holds the correctexternal memory address
• External Indirect
• Code Indirect

• MOV A,20h
• MOV A,30h
• MOV A,_at_R0
• MOVX A,_at_DPTR
• MOVX _at_DPTR,A
• MOVX _at_R0,A
• MOVC A,_at_ADPTR

125
Intel 8051 Keil C Compiler
Part 1

• Keil Compiler C51 includes extensions (for ANSI
  C) for
• Memory Types and areas on the 8051
• Memory Models
• Memory Type Specifiers
• Variable Data Type Specifiers
• Bit variables and bit-addressable data
• Special Function Registers
• Pointers
• Function Attributes

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Intel 8051 Keil C Compiler
Part 2

• Program Memory
• code specifier refers to to the 64Kbyte code
  memorychar code text ENTER PARAMETER
• Accessed by opcode MOVC _at_ADPTR
• Program Memory is read only it cannot be written
  to
• It can reside within 8051 CPU, it may be
  external, or both
• Program code, including all functions and library
  routines are stored in program memory

127
Intel 8051 Keil C Compiler
Part 3

• Data Memory
• Up to 256 bytes of internal data memory are
  available depending upon the 8051 derivate
• data refers to the first 128 bytes of internal
  memorychar data var1
• idata refers to all 256 bytes of internal data
  memorygenerated by indirect addressingfloat
  idata x,y,z
• bdata refers to 16 bytes of bit-addressable
  memoryin the internal data memory (20h to
  2Fh)char bdata flags

128
Intel 8051 Keil C Compiler
Part 4

• External Data Memory
• xdata specifier refers to any locationin the
  64KByte address space of external data
  memoryunsigned long xdata array100
• pdata specifier refers to only 1 page of 256
  bytesof external data memoryunsigned char
  xdata vector1044

129
Intel 8051 Keil C Compiler
Part 5

• Special Function Register Memory
• SFRs are declared in the same fashion as other C
  variables
• sfr (rather then char or int)sfr P0 0x80
  /Port0, address 80h/
• sfr16 access 2 SFRs as 16-bit SFR (8051
  derivatives)sfr16 T2 0xCC /Timer 2 T2L 0CCh,
  T2H 0CDh)
• sbit allows to access individual bits within an
  SFRsfr PSW0xD0sfr IE0xA8sbit EAIE7sbit
  OV0xD02sbit CY0xD7

130
Intel 8051 Keil C Compiler
Part 6

• Unique C51 Data Types
• bitstatic bit done_flag0
• sbit
• sbit EA oxAF /defines EA to be the SFR bit at
  0xAF/
• sfr(Special Function Registers, 0x80-0xFF)
• sfr P0 0x80 / Port-0, address 80h/
• sfr P2 0xA0 / Port-2, address 0A0h /
• sfr16
• sfr16 T20xCC / Timer 2 T2L 0CCh, T2H 0CDh

131
Intel 8051 Keil C Compiler
Part 7

• Memory Models
• SmallModel - all variables, by default, reside
  in the internal data memory
• All objects, as well as stack must fit into
  internal RAM
• Compact Model -all variables, by default, reside
  in one page of external data memory
• Can accommodate a maximum of 256 variables
• Slower then small model
• Large Model - all variables, by default, reside
  in external data memory
• The Data Pointer (DPTR) is used for addressing
• Memory access is inefficient
• Generates more code then small and compact model

132
Intel 8051 Keil C Compiler
Part 8

• Memory-specific Pointers
• Include a memory type specification in the
  pointer declaration
• May be used to access variables in the declared
  memory area onlychar data strint xdata
  numtablong code powtab

133
Intel 8051 Keil C Compiler
Part 9

• Function Declarations Extensions allow to
• Specify a function as an interrupt procedure
• Choose register bank used
• Select the memory model
• Specify reentrancyreturn_type funcname
  (args) smallcompactlarge reentranti
  nterrupt nusing n
• small, compact, large - memory model
• reentrant - recursive function
• interrupt - interrupt function
• using - specify register bank

134
Intel 8051 Keil C Compiler
Part 10

• Function Parameters and the Stack
• The stack pointer on the 8051 access internal
  data memory only
• C51 locates the stack area immediately
  followingall variables in the internal data
  memory
• The stack pointer access internal data memory
  inirectly
• C51 assigns a fixed memory location for each
  function parameter
• Only return address is stored on the stack
• Interrupts fuctions switch register banks
  andsave the values of few registers on the
  stack
• By default, the C51 compiler passes up to three
  arguments in registers

135
Intel 8051 Keil C Compiler
Part 11

• Passing Parameters in Registers

136
Intel 8051 Keil C Compiler
Part 12

• Function Return Values

137
Intel 8051 Keil C Compiler
Part 13

• Specifying the Memory Model for a
  Functionpragma small /default small model
  /extern int calc (char i, int b) large
  reentrantextern int func (char i, float f)
  largeextern void tcp (char xdata xp, int ndx)
  smallint mtest (int i, int y) /small
  model/ return (iy yi func(-1,
  4.75)int large_func (int i, int k) large
  /large model/ return (mtest(i,k) 2)

138
Intel 8051 Keil C Compiler
Part 14

• Specifying the RegisterBank for a Functionvoid
  rb_function (void ) using 3 ...
• The using attribute affects object code as
  follows
• The currently selected register bank is saved on
  stack
• The specified register bank is set
• The former register bank is restored before the
  function is exited
• Register banks are useful when processing
  interrupts orwhen using a real-time operating
  system
• The using attribute may not be used infunctions
  that returns a value in registers

139
Intel 8051 Keil C Compiler
Part 15

• Register Bank Access
• The REGISTERBANK control directive allows you to
  specify which default register bank to use
• Upon reset, 8051 loads the PSW with 00h, which
  selects register bank 0. To change this, you
  sholud
• Modify the startup code to select a different
  bank
• Specify the REGISTERBANK control directive along
  with the new register bank number
• By default, C51 generates code that accesses the
  registers R0-R7 using absolute addresses
• To make a function insensitive to the current
  bank, it must be compiled using the NOAREGS
  control directive

140
Intel 8051 Keil C Compiler
Part 16

• Interrupt Functions void timer0 (void) interrupt
  1 using 2 if (interruptcnt
  4000) second Interruptcnt0
• The interrupt attribute takes an argumentan
  integer constant in the 0 to 31 value range
• The interrupt attribute affects object code as
  follows
• The contains of SFR ACC, B, DPH, DPL and
  PSW,when required, are saved on stack
• All working registers are stored on stack if a
  register bank is not specified
• SFRs and working registers are restored before
  exiting function
• The function is terminated by 8051 RETI
  instruction

141
Intel 8051 Keil C Compiler
Part 17

• Reentrant Function can be shared by several
  processes at the same time.
• When a reentrant function is executing, another
  process can interrupt it and then begin to
  execute that same function. The reentrant
  functions may be called recursively
• int calc (char i, int b) reentrant
• int x
• xtablei
• return (xb)
• Reentrant functions can be called simultaneously
  by two or more processes.
• Reentrant functions are often required in
  real-time applications or when interrupt and
  non-interrupt code must share a function.

142
Intel 8051 Keil C Compiler
Part 18

• Functions may be selectively defined as
  reentrant, using the reentrant attribute.
• For each reentrant function, a reentrant stack
  area is simulated in internal or external memory.
• The following rules apply to reentrant functions
• bit type arguments or local variables may not be
  used
• must not be called from alien functions or using
  alien attribute
• may have other attributes like using or interrupt
• return addresses are stored in the 8051 hardware
  stack
• functions using different memory models may be
  intermixed
• each of three reentrant models (small, compact
  and large) contains its own reentrant stack and
  SP

143
Intel 8051 Keil C Compiler
Part 19

• Control directives are used to control the
  operation of the compiler and can be specified
  after the filename on the command line or within
  a source file using the pragma directive
• C51 testfile.c SYMBOLS CODE DEBUG
• or
• pragma SYMBOLS CODE DEBUG
• Directive categories
• source controls define macros on the command line
  and determine the name of the file to be
  compiled)
• object controls affect the form and content of
  the generated object module allow you to specify
  the optimizing level or include debugging
  information in the object file
• listing controls govern various aspects of the
  listing file (format and specific content)

144
Intel 8051 Keil C Compiler
Part 20

• The C51 is an optimizing compiler.
• The C51 provides six different levels of
  optimizing
• constant folding, simple access optimizing, jump
  optimizing
• dead code elimination, jump negation
• data overlaying
• peephole optimizing
• register variables, extended access optimizing,
  local common subexpression elimination,
  case/switch optimizing
• global common subexpression elimination, simple
  loop optimizing
• loop rotation

145
Intel 8051 Keil C Compiler
Part 21

• General optimizations
• constant folding several constant values
  occurring in an expression or address calculation
  are combined as a constant
• jump optimizing jumps are inverted or extended
  to the final target addresses when the program
  efficiency is thereby increased
• dead code elimination code which cannot be
  reached is removed
• register variables automatic variables and
  function arguments are located in registers when
  possible
• parameter passing via registers a maximum of
  three function arguments can be passed in
  registers
• global common subexpression elimination
  identical subexpressions or address calculations
  that occur multiple times in a function are
  calculated only once

146
Intel 8051 Keil C Compiler
Part 22

• 8051 - specific optimizations
• peephole optimization complex operations are
  replaced by simplified operations when memory
  space or execution time can be saved as a result
• extended access optimizing constants and
  variables are included directly in operations
• data overlaying data and bit segments of
  functions are overlaid with other data and bit
  segments by the linker/locator
• case/switch optimization any switch and case
  statements are optimized by using a jump table or
  string of jumps

147
Intel 8051 Keil C Compiler
Part 23

• Options for code generation
• OPTIMIZE(SIZE) common C operations are replaced
  by subprograms, thereby reducing the program code
• NOAREGS C51 no longer uses absolute register
  access program code is independent of the
  register bank
• NOREGPARAMS parameter passing is always
  performed in local data segments

148
Intel 8051 Keil C Compiler
Part 24

• You can easily interface C51 to routines written
  in 8051 assembler
• For an assembly routine to be called form C, it
  must be aware of the parameter passing and return
  value conventions used in C
• Function parameters
• By default C functions pass up to three
  parameters in registers. The remaining parameters
  are passed in fixed memory locations.
• Functions that pass parameters in registers are
  prefixed with the underscore character
  (_functionName)

149
Intel 8051 Keil C Compiler
Part 25

• Parameter passing in registers
• arg.no. char, 1byte ptr. Int, 2byte
  ptr long,float gen.ptr
• 1 R7 R6R7 R4-R7 R1-R3
• 2 R5 R4R5 R4-R7 R1-R3
• 3 R3 R2R3 R1-R3
• func1 (int a) - a is passed in R6 and R7
• func2 (int b, int c, int d) - b is passed in
  R6