Improved Long-term Reliability Evaluations for DoD Microelectronics

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Improved Long-term Reliability Evaluations for
DoD Microelectronics

• 7th MAPLD International Conference
• Ronald Reagan Building and
• International Trade Center
• Washington, DC
• September 8-10, 2004

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Outline

• Blame it on Moore?
• DoD Reliability Concerns
• Key Failure Mechanisms
• DMEAs Improved Reliability Efforts
• Summary

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Moores Law

• IC complexity roughly doubles every 2 years
  Gordon Moore, 1965

• Creativity has overcame technical barriers
• Lithography
• Cu
• Low-k dielectrics

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Effects of Scaling

• Scaling results in many factors leading to infant
  mortality
• Higher density
• More layers
• Thinner gate oxides
• Unproven materials and processes

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DoD Reliability concerns

• COTS ICs in a MIL environment
• FPGA, uP, memory, ASICs
• Need for extended temperature range
• VERY long service life (relative to consumer)
• Use of parts outside intended markets
• Less manufacturer support and data on parts
• DoD small player little data/support
• Competition and proprietary processes
• Uncertainty of new materials and processes
• Reduced margins

Margin is performance left on the table
Steve Huber, Intel, DMSMS 2001
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Some Key Failure Mechanisms

• Design and Manufacturing Defects
• Layout
• Metalization
• Oxide
• Bonding
• Semiconductor Wearout
• Electromigration
• Hot Carrier Damage
• Gate Oxide Failure TDDB

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Manufacturing Defects

• Scaling pushes the limits of manufacturing
• Defects lead to infant mortality
• Design rule violations
• Current density
• Layout
• Fabrication defects
• Voids in conductors
• Pinhole defects in oxide
• Non-uniformity
• Stress voiding

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Electromigration

• Metal formation or voids in/between interconnects
• Diffusion of metal atoms along a conductor in the
  direction of electron flow
• Increases with
• Increased current density
• Higher temperature
• Interconnect density

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Hot Carrier Degradation

• High electric field for carriers in depletion
  region
• Carriers at drain end of depletion region gain
  sufficient energy to inject into the gate oxide
  and cause fundamental parameter shifts
• transconductance
• Threshold voltage
• Decreased dimensions increase electric fields
• Temperature has little effect
• Higher operating voltage increases field thus
  increasing hot carrier effects

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Gate Oxide Failure

• Time dependent dielectric breakdown (TDDB)
• Gate oxide fails when conductive path forms in
  the dielectricshorting the device
• Lifetime decreases exponentially with increasing
  electric field
• Thin oxides result in shorter lifetimes
• Nigam1 suggests lifetimes of 8-9 years (Gox33A,
  3.3V)
• Unknowns relative to high-k dielectrics
• Unknowns for thin gate oxides (lt40A)
• Pin hole oxide defects increase failures

• 1. Nigam, T. (1999). A fast and simple
  methodology for lifetime prediction of ultra-thin
  oxides. IRPS Proceedings, pp. 381-388.

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DMEA Reliability Efforts

• MIL-HDBK-217
• Failure Rate-based reliability models (UofMD)
• OIM and EBSD inspections
• Better manufacturer data AQEC

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MIL-HDBK-217F

• Outdated and unsupported since Perry memorandum
  in 1994
• Still required by many MIL contracts
• Appendix B does address EM, TDDB, Hot Carrier
  effects (limited)
• Based on RADC VHSIC Reliability Prediction report
• But, still based on 1990s parameters
• Sample tables range from 0.8um to 1.2um feature
  size
• No provisions for gate oxide thickness or
  material
• GEIA G-12 and DMPG will discuss MIL-HDBK-217 with
  OSD/DSPO at upcoming September meeting

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MIL-HDBK-217F

• Many users and tools do not incorporate Appendix
  B
• Item SW has recently incorporated App B into its
  reliability tool

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Failure Rate-based Reliability Models

• Consortium effort with AVSI
• Members include Boeing, DoD, FAA, Goodrich,
  Honeywell, Smiths
• Principle research by U of MD (Dr. Joseph
  Bernstein)
• Addresses semiconductor reliability (wearout) in
  an aerospace application
• Failure based reliability models
• vs. industry degradation models (BERT et. al.)
• Model operating parameters of IC
• Apply custom POF models to each component at the
  modeled operating parameters
• Validate POF model parameters with actual testing

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OIM and EBSD

• Orientational Imaging Microscopy (OIM)
• Electron BackScatter Diffraction (EBSD)
• 3 dimensional evaluation of
• metal interconnects
• Grain evaluations of
• conductors

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Electron Backscatter Diffraction Pattern

• Electron backscatter diffraction pattern (EBSD)
  is a method to measure orientation of crystalline
  material from a small area
• The sample is tilted in SEM to approximately 70
  degrees. The diffraction pattern is imaged on a
  phosphor screen. The bands in the pattern
  represent the reflecting planes in the
  diffracting crystal volume. Thus, it shows the
  orientation of the diffraction crystal lattice.

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Prediction Using EBSD

• Prior work evaluated COTS ICs using traditional
  methods
• Cross sections
• Top down
• X-ray
• Either of the physical analysis methods is hit
  or miss due to circuit complexity but EBSD is
  quantitative
• Conductors carrying current can act as micro
  beams
• These conductors, under DC conditions, exhibit
  migration of metal ions
• Additionally, for Cu damascene interconnects,
  deposition process is critical and not always
  reproduced from lot-to-lot
• Hence, grain size distribution is not the same
  from lot-to-lot
• Does this make a difference? Probably yes.
• Grain size and distribution will be a key area of
  investigation
• Twins and misorientation will also be evaluated

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Interconnect Isolation
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Current Work

• Investigate EBSD as key identifier of IC quality
• Grain size and distribution
• Strain distribution
• Misorientation and twins formation
• Analysis before and after stress

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AQEC

• Aerospace Qualified Electronic Component (AQEC)
• AIA/GEIA G-12/Aerospace Process Management
  Committee(APMC) initiative
• ISSUE
• Fewer and fewer MIL parts offerings
• Cost IS and issue
• Designers need better parts and more data
• Upscreening COTS is risky at best
• STATUS
• Draft AQEC specification in work by AQEC WG

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AQEC goals

• Manufacturer qualified components for aerospace
  applications
• Extended temperature
• Reliability and qualification data
• Product Change Notices
• Design stability
• Little or no increase in cost over COTS offerings

IC manufacturers are best suited to specify their
components operating capabilities
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AQEC - Whos Involved ?
Airframe Integrators Boeing, Lockheed Martin,
Northrop Grumman
DoD NAVAIR, DSPO, AWACS, AMCOM, JCAA, DUSD(LMR)

Avionics OEMs Honeywell, BAE, Smiths, Rockwell
Collins, Goodrich
Part Manufacturers Motorola, AMI, Micron, Texas
Instruments, IBM, Intel, Xilinx, National, LSI
Logic, Vishay-Siliconix, Linear Technology,
Altera, Philips, Analog Devices
Others NASA, FAA, COG, G-12, EIA, SIA, JEDEC,
AIA, AVSI, DSCC
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Summary

• DoD is concerned about long-term reliability for
  fine feature size microelectronics
• FPGA
• Microprocessors
• Memory
• Update and support for MIL-HDBK-217 or
  replacement
• Investigating failure rate-based modeling of IC
  reliability for various design and foundry
  processes
• Investigating novel metal reliability evaluation
  methods using OIM and EBSD
• Support of AQEC to provide availability of
  better parts and data for designers
• At this time there are many more questions than
  answers