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CLASS

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Some materials from Alnuweiri * * * * Digital Design using VHDL and Verilog Marek Perkowski Department ... of Sums (POS) using NOR/NOR Digital System Design: ... – PowerPoint PPT presentation

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Title: CLASS


1
  • CLASS
  • GRADING
  • HOMEWORKS
  • PROJECTS
  • REVIEW OF DIGITAL LOGIC

2
Digital Design using VHDL and Verilog
  • Marek Perkowski
  • Department of Electrical and Computer Engineering
  • Portland State University

3
Introduction
  • Administration
  • About Review
  • RASSP Program
  • Why VHDL?
  • Flip-Flops (see ECE 271 class slides)
  • Shift Registers
  • Generalized Register
  • Pipelined Sorter

4
Administration
  • Instructor Prof. Marek A. Perkowski
  • Course Information
  • My home page http//ee.pdx.edu/mperkows
  • Computer Engineering web site
  • http//ece.pdx.edu

5
Administrative
  • Office
  • FAB room 160-05
  • Office Hours
  • Fridays 6 pm - 10 pm - meetings in FAB, room 150
  • Other Times by Appointment
  • Office Phone
  • (503)725-5411 (Answering Machine)

6
Administrative
  • Email
  • mperkows_at_ee.pdx.edu
  • Students with Disabilities
  • If you need special assistance, please inform me
    soon so that we can work something out.
  • There is a milestone chart available on the class
    web site.

7
Grading
  • HW 35
  • Assignments are on the web, may be changed. If
    changed, I will inform you. Usually these are
    mini-projects. You may be asked to present them
    in class.
  • Final Project 65
  • You will present it in class
  • No exams

8
Grading
  • Attendance at Lecture
  • Not graded, but recommended.
  • Attendance at Friday meetings not graded, come if
    you can.
  • Makeup Exams
  • Makeup homeworks or exams are not given.
  • Project should be completed before end of the
    class

9
More details on this year class
  1. There are two homeworks 35
  2. Project is 65
  3. No exam, no midterms.
  4. You will need to make a good quality presentation
    of project.
  5. I may ask you to present your homework as well.
  6. A homework or both homework may be part of your
    final project.
  7. A group can have from one to three people.
  8. Each team member is responsible for part of
    coding no person can have a grade in this class
    if he/she has not done coding and simulation.

10
More details on this year class
  • Every team has to do simulation using Modelsim.
  • Most of you have free CAD software, other should
    contact CATs or Philip or me.
  • Good and complete software comes also with
    Wakerly book.
  • A more ambitious project involves compiling your
    simulated design to FPGA you should have your
    own FPGA (around 250 dollars).
  • A more ambitious project involves Veloce
    Emulation.
  • Additional one credit or more are possible
    related to this class.
  • There are chapters of our book available
  • http//web.cecs.pdx.edu/mperkows/CLASS_VELOCE_201
    1/index.html
  • More chapters will be added soon.
  • This is very much related to projects from the
    class.

11
Homeworks
  • Homeworks Require Use of VHDL
  • Always you have to simulate the circuit
  • You may be asked to synthesize it also.
  • Mentor Graphics Tools
  • contact support (cat) people
  • use any lab that is available. Work at home.
  • use addpkg
  • We use Modelsim for simulation and
    LeonardoSpectrum for synthesis. Synthesis is
    mandatory for the project.

12
Slides
  • My slides are based on at least 5 books, slides
    from Internet and my industrial experience, on
    top of teaching this class since 1989. You can
    learn all you need if you read slides in detail.
  • Not always I will cover all slides in class. In
    such case you have to complete reading slides for
    this week at home.
  • You can learn a lot from previous homeworks and
    projects that are posted.

13
Required and Additional Textbooks
  • Required and recommended
  • VHDL and FPLDs. Zoran Salcic. CD ROM included.
    Kluwer Academic Publishers
  • see my web page
  • Additional
  • The Designers Guide to VHDL
  • Peter J. Ashenden
  • Morgan-Kaufman
  • ISBN 1-55860-270-4 (paperback)
  • LOC TK7888.3.A863
  • Dewey Decimal 621.392--dc20
  • 1996

14
Resources
  • IEEE Standard 1076-1993
  • find using search engines on WWW
  • Use my WWW Page resources, too much to digest.
  • IEEE Interactive VHDL Tutorial
  • On-line on Computer Engineering Home page
  • http//cpe.gmu.edu
  • password protected

15
Resources
  • Our Book
  • Cypress Semiconductor (Warp release 5.x)
  • PC-based
  • 99 with textbook
  • Oriented towards Their PLD FPGA devices
  • VHDL Subset simulator
  • Xilinx FPGA
  • Student edition
  • Schematic, FSM, VHDL

16
Honor Code
  • You Are Encouraged to Collaborate With Other
    Students in Projects.
  • Final VHDL code for each Homework should be done
    by yourself.
  • In Final Project, each file should have at the
    top student name of the student responsible for
    this part of code.

17
Remind the class.
  • Your webpage
  • List of your names with interests and
    experiences. Previous design projects that you
    have done.
  • Any experience in robotics?
  • Any experience in pipelined and systolic
    processors?
  • Any experience with image processing?
  • Previous VHDL or Verilog projects.
  • C experience
  • Other languages like LISP, Prolog, Basic, etc.
  • I will intentionally repeat the most important
    parts of material or ideas. I believe in real
    understanding of material by students and good
    understanding of fundamentals is most important
    for me.
  • You have to understand the combinational logic,
    flip-flops, registers, state diagrams,
    pipelining, ALU, etc.

18
Homework 1
  1. Simple Satisfiability Machine
  2. Simple Petric Function Oracle based machine
  3. Any type of Sorter
  4. Fibonacci sequence generator
  5. GCD
  6. LCM
  7. Any other controller from CU and DP.
  8. Any other oracle, SENDMOREMONEY, graph
    coloring, etc.

These are just examples, more projects will be
added, you can propose your own project.
19
High Level System DesignPossible VHDL Projects
for Spring 2012
  • Marek Perkowski

20
ORACLES
21
Oracle Based Homeworks and Projects
  1. SAT solvers
  2. Petrick Function and similar decision function
    solvers
  3. Graph Coloring Optimizing Architecture
  4. Image Matching by maximum clique.
  5. (reserved for Alan Cheng) General Solver for
    Cryptography. Problems like SENDMOREMONEY.
  6. Universal Sudoku Machine
  7. Hardware solvers for Generalizations of Sudoku

22
Projects for year 2012 Oracles
  1. Graph Coloring (optimized)
  2. FPRM learning
  3. Logic Puzzles
  4. Error Correcting codes design
  5. Traveling Salesman
  6. Any other oracles with practical use

These are just examples, more projects will be
added, you can propose your own project.
23
ROBOTICS
24
Robotics Related VHDL projects
  1. State Machine controller that learns from
    examples.
  2. Evolutionary algorithms (such as Genetic
    Algorithm) in hardware
  3. Backtracking search optimizer for mazes.
  4. Early Vision system for a robot.
  5. Camera interface.
  6. Microphone interface.
  7. Interfaces for motion control for servo motors,
    DC motors and Stepper Motors.
  8. Subsumption architecture.
  9. Inverse kinematics solver.
  10. General purpose robotic FSM controller with
    timers, stacks and decision modules.
  11. Probabilistic State Machine and Hidden Markov
    Model for a robot.
  12. Converter of human speech to robot head/neck
    motion.

25
Projects for year 2012 Robotics
  1. Speech Recognition for a robot (new)
  2. Rough Set Machine (continuation - Torrey Lewis)
  3. Convolutional Image Processor (continuation)
  4. Controller of a Robot (new)
  5. Evolvable Hardware (new)

These are just examples, more projects will be
added, you can propose your own project.
26
Cellular Automata
27
Projects for year 2012 Cellular Automata and
Robotics
  1. Mandelbrot Set with quaternions and octonions
  2. Robot Vision with morphological algebras
  3. Galois Field Arithmetics for robot vision
  4. Neural Net for a robot
  5. PID controller for a robot
  6. Sum of Product minimization for a robot
  7. Decision trees in hardware for robot
  8. Car model control
  9. Logic Decomposition

These are just examples, more projects will be
added, you can propose your own project.
28
Cellular Automata
  1. Variants of Game of Life
  2. Biosystems simulation
  3. Quantum Physics simulation
  4. Firing Squad architecture
  5. Dining Philosophers and applications.

29
Projects for year 2012 Cellular Automata and
Robotics
  1. Hidden Markov Model
  2. Kalman Filter for robot
  3. Particle Filter for robot obstacle avoidance
  4. Genetic Algorithm in hardware

These are just examples, more projects will be
added, you can propose your own project.
30
Computer Architecture
31
Computer architecture
  1. Computer Graphics
  2. LISP machine
  3. Prolog Machine
  4. General Hardware Search Solver
  5. Contents Addressable Memory architecture with
    internal processing for tautology and similar
    problems.

32
Advanced Digital Design, Modal Logic
  1. Muddy Children and Modal/Temporal Logic.
  2. Narrow Bridge Problem (is this CA?)
  3. Your own invention related to Modal or Temporal
    Logic.

33
Pipelined and Systolic Processors
  1. Sorters
  2. Sorters/absorbers
  3. Cube calculus data flow machines.

34
Projects for year 2012 Transforms
  1. Hough Transforms
  2. Radon Transforms
  3. Fast Fourier Transform
  4. Hadamard
  5. Haar
  6. Adding
  7. Arithmetic
  8. Gabor

These are just examples, more projects will be
added, you can propose your own project.
35
Review
36
Review
  • Mealy and Moore
  • Registered Output
  • Rabin-Scott

37
Digital System Representation
38
Basic Logic Functions
39
Logic Synthesis Using AND, OR and NOT gates
40
Function Minterms and Maxterms
Discuss generator of all functions of certain
type, use MUX as example
41
Example 3-variable function
42
Example 3-variable function
43
NAND, NOR, and De Morgans Theorem
44
Realizing Sum of Products (SOP) using NAND/NAND
45
Realizing Product of Sums (POS) using NOR/NOR
46
Digital System Design Adder
47
Iterative Structure of Adder
48
Full Adder
49
Full Adder Realization
50
Implementation Using Multiplexers
51
Binary Decoder Circuits
52
A 2-to-4 Decoder with Enable
53
FA implementation using Decoders
54
D Flip-Flop
This is a synchronized D ff with negated output
55
Sequential (Bit-Serial) Adder
56
Sequential Adder
57
Behavioral Model of Sequential Adder
All synchronized by one clock
58
To discuss on white-board
  • Sorting data flow
  • Pipelined circuit from it
  • Butterfly combinational circuit from it
  • Sequential controller from it
  • The concepts
  • Combinational circuit
  • Finite State machine
  • Shifting circuits, starting from Moebius Counter.
    (Johnson)
  • Cooperating FSMs.
  • Iterative Circuit
  • Pipelined circuit
  • Systolic circuit
  • Cellular automaton

59
For students to remember
  • SOP and POS
  • Nand, Nor and De Morgan
  • Multiplexer
  • Decoder
  • Adder
  • Iterative circuit for adder
  • Other iterative circuits
  • D flip-flop
  • Flip-flop and register without and with enable.
  • Use of enable in other circuits
  • Sequential versus parallel circuits trade-off.

60
Some materials from Alnuweiri
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