Chapter 3.2 : Virtual Memory

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Chapter 3.2 Virtual Memory

• What is virtual memory?
• Virtual memory management schemes
• Paging
• Segmentation
• Segmentation with paging
• Page table management

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Problems with Memory Management Techniques so far

• 1. Unused (wasted) memory due to fragmentation
• 2. Memory may contain parts of program which are
  not used during a run (ie., some routines may not
  be accessed in that particular run)
• 3. Process size is limited with the size of
  physical memory

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Virtual Memory (VM)
Virtual memory of process on disk
Map (translate) virtual address to real
Real memory of system
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Virtual Memory (VM)

• VM is conceptual
• It is constructed on disk
• Size of VM is not limited (usually larger than
  real memory)
• All process addresses refer to the VM image
• When the process executes all VM addresses are
  mapped on to real memory

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Did We Solve the Problems?

• 1. Unused (wasted) memory due to fragmentation
  (Well see!)
• 2. Memory may contain parts of program which are
  not used during a run
• YES! Virtual memory contents are loaded into
  memory on demand
• 3. Process size is limited with the size of
  physical memory
• YES! Process size can be larger than real memory

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(Pure) Paging

• Virtual and real memory are divided into fixed
  sized pages
• Programs are divided into pages
• A process address (both in virtual real memory)
  has two components

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Interpretation of an Address

• 16 bits for addressing means that the memory
  addressed is 64K bytes (0000 -FFFF)
• Suppose page size is 4K bytes (12 bits)
• The virtual memory has 16 pages (4 bits)
• Real memory can have at the most 16 pages
• Example
• address 7 F B C
• 0111 1111 1011 1100

Page
Offset
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The relation between virtual addresses and
physical memory addresses

• 64K Virtual Memory
• 32K Real Memory

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Paging (Cont.)

• When process pages are transferred from VM to
  real memory, page numbers must be mapped from
  virtual to real memory addresses
• This mapping is done by software hardware
• When the process is started only the first page
  (main) is loaded. Other pages are loaded on demand

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Virtual Memory Memory Management Unit

• The position and function of the MMU

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Note that virtual address is 16 bits (64K
virtual memory) but the physical address is 15
bits (32K real memory)

• Internal operation of MMU with 16 4 KB pages

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Page Tables

• Index of page table is the virtual page

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Page Table Entry Fields

• Validity bit is set when the page is in memory
• Reference bit is set set by the hardware whenever
  the page is referred
• Modified bit is set whenever the page is modified
• Page-protection bits set the access rights (eg.,
  read, write restrictions)

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Address Mapping in Paging
Real memory address
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Address Mapping in Paging (Cont.)

• During the execution every page reference is
  checked against the page map table entry
• If the validity bit is set (ie., page is in
  memory) execution continues
• If the page is not in memory a page fault
  (interrupt - trap) occurs and the page is fetched
  into memory
• If the memory is full, pages are written back
  using a page replacement algorithm

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Memory Management Problems Re-visit due to
paging

• 1. Unused (wasted) memory due to fragmentation
• ONLY on the last page (Page Break)
• 2. Memory may contain parts of program which are
  not used during a run
• Virtual memory contents are loaded into memory on
  demand
• 3. Process size is limited with the size of
  physical memory
• Process size can be larger than real memory
• Furthermore, program does not occupy contiguous
  locations in memory (virtual pages are scattered
  in real memory)

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Segmentation

• Pages are fixed in size, segments are variable
  sized
• A segment can be a logical entity such as
• Main program
• Some routines
• Data of program
• File
• Stack

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Segmentation (Cont.)

• Process addresses are now in the form

• Segment Map Table has one entry for each segment
  and each entry consist of
• Segment number
• Physical segment starting address
• Segment length

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Segmentation (1)

• One-dimensional address space with growing tables
• One table may bump into another

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Segmentation (2)

• Allows each table to grow or shrink, independently

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Segmentation (3)

• Comparison of paging and segmentation

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Implementation of Pure Segmentation

• (a)-(d) Development of fragmentation
• (e) Removal of the fragmentation by compaction

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Problems with Segmentation

• Similar problems in dynamic partitioning
• Fragmentation in real memory
• Relocation is necessary for compaction

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Segmentation with Paging

• Segmentation in virtual memory, paging in real
  memory
• A segment is composed of pages
• An address has three components

• The real memory contains only the demanded pages
  of a segment, not the full segment

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Addressing in Segmentation with Paging
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Segmentation with Paging MULTICS (1)

• Descriptor segment points to page tables
• Segment descriptor numbers are field lengths

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Segmentation with Paging MULTICS (2)

• A 34-bit MULTICS virtual address

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Segmentation with Paging MULTICS (3)

• Conversion of a 2-part MULTICS address into a
  main memory address

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Segmentation with Paging MULTICS (4)

• Simplified version of the MULTICS TLB
• Existence of 2 page sizes makes actual TLB more
  complicated

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Segmentation with Paging Pentium (1)

• A Pentium selector

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Segmentation with Paging Pentium (2)

• Pentium code segment descriptor
• Data segments differ slightly

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Segmentation with Paging Pentium (3)

• Conversion of a (selector, offset) pair to a
  linear address

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Segmentation with Paging Pentium (4)

• Mapping of a linear address onto a physical
  address

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Segmentation with Paging Pentium (5)
Level

• Protection on the Pentium

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How Big is a Page Table?

• Consider a full 2 32 byte (4GB) address space
• Assume 4096 byte (2 12 byte) pages
• 4 bytes per page table entry
• The page table has 2 32/2 12 ( 2 20 ) entries
  (one for each page)
• Page table size would be 2 22 bytes (or 4
  megabytes)

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Problems with Direct Mapping?

• Although a page table is of variable length
  depending on the size of process, we can not keep
  them in registers
• Page table must be in memory for fast access
• Since a page table can be very large (4MB), page
  tables are stored in virtual memory and be
  subjected to paging like process pages

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How to Solve?

• Two-level Lookup
• Inverted Page Tables
• Translation Lookaside Buffers

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Two-Level Lookup
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Two-Level Lookup (Cont.)
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Two-Level Lookup (Cont.)

• A process is represented by one or more entries
  of the page directory (ie., several page tables)
• Typically a page table size is set as one page
  which makes swapping easier
• This is one of the addressing schemes used by
  Intel family of chips (Intel chips can use
  paging, segmentation or a combination of both)

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Two-Level Lookup (Cont.)
Second-level page tables
Top-level page table

• 32 bit address with 2 page table fields
• Two-level page tables

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Inverted Page Tables
PID
Page
17
21
76
23
Page 101
Process 17
Hash 2
3
32
213
Page Frame Table
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Inverted Page Tables (Cont.)

• The virtual page number is hashed to point to a
  hash table
• The hash table contains a pointer to the inverted
  page table
• Inverted page table contains page table entries
  (one for each real memory page)
• Entries having the same hash codes are chained

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Inverted Page Tables (Cont.)

• A fixed portion of memory is used for mapping
  regardless of the number of processes or virtual
  pages
• This approach is used by IBMs AS/400 and RISC
  System/6000 computers

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Translation Lookaside Buffer
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Translation Lookaside Buffer (Cont.)

• Translation lookaside buffer (TLB) is a cache for
  page table entries
• TLB contains page table entries that have been
  most recently used
• Whenever the page table is referred (TLB miss),
  the page table entry is also copied to the TLB
• TLB is usually an associative memory (content
  addressable memory)

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TLBs Translation Lookaside Buffers

• A TLB to speed up paging