Profiles in Power: Optimizing Real-Time Systems for Power As well as Speed (IPS), Response Latency and Cost

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Profiles in Power Optimizing Real-Time Systems
for PowerAs well as Speed (IPS), Response
Latency and Cost

• Graham Hellestrand
• Mahdi Seddighnazhad
• James Brogan
• VaST Systems Technology Corporation

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Wireless Trends

• Key Focus Low Cost, Power Reduction and
  Increased Features
• Competitive positionsmust be maintained
• Product complexity isincreasing
• Hardware growth
• Software growth
• Critical Program Schedules
• Market windows must be hit
• Revenue opportunitiesmust be captured
• Burden has moved to designand development

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Automotive Trends

• Key Focus Increased Quality/reliability,
  Performance and Cost Reduction
• Required to be awardedthe business
• Critical Program Schedules
• MY launches must be kept
• Product Complexity Is Starting to Increase
• Hardware growth
• Softwaregrowth
• Burden has moved todesign and development

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The Metric Power Reducing in power regardless
of the effect on other optimization factors is of
limited value.

• Example
• Saving 50 power
• While Yielding
• 50 speed hit and/or
• Failure to meet response latency specifications
• Is likely to be a unacceptable in the marketplace

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Implications

• Real-time software architecture and development
  needs to be subject to a rigorous optimization of
  an appropriate objective function, based on
• Power
• Speed
• Event response latencies
• Examples interrupts, exceptions
• Cost approximated by
• Cache sizes
• Memory sizes and hierarchies

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System Architecture OptimizationSoftware
ArchitecturePlatform ArchitectureReal-world
interaction architectureProcessor
µ-architectureEmpirical experimentation
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Architecture Addresses the Whole System
Buses Bridges
Devices
VPMs Peripheral Devices
Structures
Architecture
RF, Mechanical, Physical
Virtual Prototype
Sub- systems
Evaluation, Exploration
Systems
Platform
Appli- cations
Behav.
Middleware, Comms
Software
Hardware
Operating Systems
RTL
Device Drivers
Physical
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Optimization effectSoftware Architecture
Design1st Order Effect on system performance
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Software Architecture Design
UML, Simulink, C, C,
Create
Compile
Assemble

• Monitor prototype internals
• Cache hits/misses
• Bus transactions
• Processor performance
• Memory usage
• Interrupt latency
• Trigger hardware and software debuggers
• Example usage analyze processor and platform
  power
• Make intelligent tradeoffs between power,
  performance and cost

Link
HW
Load
VaST VSP
Debug Monitor
SW IDE
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Optimization effectPlatform Architecture
Design1st Order Effect on system
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Typical 3G Cell Phone Controller3 processors, 12
buses, 10 bus bridges, 70 peripherals
VaST Virtual System Prototype (model)
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Optimization effectReal-world Interaction
Architecture1st Order Effect on system
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AutomotivePower-train Control
Igniting fuel under pressure at the wrong part of
the cylinder stroke Results in spectacular
destruction of the engine (and maybe the
experimenter)
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Optimization ofProcessor µ-architecture 2nd /
3rd Order Effect(apart from caches buffering)
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Pipeline Specification
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Generic Single Pipeline Operation
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Pre-Silicon System Design Process
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System Development Process
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Electronic System Design Process

• System architecture ? Virtual Prototype (timing
  accurate)
• Software Hardware design ? Virtual System
  Prototypes (high speed)

Evaluate architectures of candidate designs using
real software applications
Architecture
Virtual Prototype
Hardware development
Software development
Develop behavioral-level executable specification
and verify RTL
Design, develop and debug software before silicon
or hardware prototypes are available
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So What Performance can we get from a Timing
Accurate VSPon a Single Processor Host?That
is how useful are these things?
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VSP Computation PerformanceMultiple Independent
Platforms
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Results - Computational Performance Study
Platform dominated study As Virtual System
Prototypes (VSPs), with the processors having
software and data resident in cache, are switched
into the simulation (Pink line), the sharing of
host cycles between the processor and the
hardware (purple line) of each VSP stays in
proportion for each additional VSP activated. The
frequent switching between VSPs, each having a
processor and hardware that also share the host
cycles, also increases the Simulation overhead
(blue line).
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VSP with TLM Bus Matrix
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Results Bus Matrix Performance
Communications and computation sharing study
This is a multi-variable study measuring
simulation performance of a system having
transactions of various sizes (1024, 64 and 4
bytes) being transmitted at a high rate over a
complex switch to which are attached two SC1200
processors. Initially no processors are activated
and each is then successively activated. The bar
chart is best read as a sequence of 3 pairs
(Transaction / Headroom (MIPS) into the slide.
As transactions become progressively smaller,
there is relatively more work to be performed by
the model to transmit and receive them. The
Headroom measure is the amount of available host
cycles for further simulation. As more processor
are activated and the transaction size is
reduced, the available headroom diminishes.
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Study 4 VSP Interrupt Handling Automotive
Benchmark, Feb 2004
Capability or a VSP under interrupt loads This
is a relatively simple experiment that shows the
performance of a single processor Virtual System
Prototype under increasingly stressful rates of
processing asynchronous events (interrupts). Even
at high interrupt rates (every 3,750 cycles is
equivalent to a 12 cylinder engine running at
20,000 RPM and producing an interrupt every 10
degrees of crank-angle) the VPM is capable of
simulating high software execution rates (4 MIPS)
while handling the interrupts.
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Back to Building Systems
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It is all about optimization, stupid!
Specifications
H-type Respecifier
Very Smart System Instantiator
Software
Power Consumption
Asynch-Signal Response Latency
Speed
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Typical 2.5G Wireless Systemsbuilt using
aVirtual System Prototype
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Virtual PrototypingMobile Handset Development
Full System Development Architecture, Software,
Hardware, I/F
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Virtual PrototypingMobile Handset Development

• Virtual Chip with Specification
• Executable Hardware Specification
• Accuracy Bit true cycle accurate
• Control Software Debugger(s)
• Performance VaST VP up to 50MHz
• Early Software Development Platform
• Early System Simulation Platform
• Very High System Reliability Faster
  Time To Market

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Wireless VP Benefits

• Early Design Feedback in Semiconductor
  Development Process
• Enabled 1st Pass Silicon Success
• Eliminated Costly 2nd Silicon
• Provided Complete SoftwareDevelopment
  Environment 9 Months Prior to Silicon
• Resulted in a Better QualityProduct 5 Months
  EarlierThan Standard DevelopmentProcess
• Advanced Debugging
• Multi-Core debugging
• ARM926 (ADS 1.2)
• TeakLite (DSP group)
• Complete system visibility
• S-GOLD programmer model
• Bus status Interrupt behavior
• System cycle count, monitors
• I/O Test Bench Support
• Open Model Extension

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Concurrent Bus Activity
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Observations on Optimizing Simulated Systems

• Observation
• Complex engineering systems like natural
  systems
• Have a large number of factors that may affect
  them
• Exhibit similar degrees of opaqueness in direct
  observation
• Require reduction in data to understand them
• As susceptible to optimization through directed
  experimentation, unlike natural systems
• Variability in simulated systems is induced by
  enabling relatively small random variations in
  pervasive factors, such as
• Delays in communications structures and signal
  lines
• Clock frequency
• Power consumption metrics
• over different simulation runs.

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Optimizing forPower and Performance

• Separated Functions

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General Form of Multi-Objective Optimization
EquationCharacterize an objective function in
terms of events directly measurable from the VSP
Problem Huge volume of data some of which may be
highly correlated with other data leading to
multiple counting and unreliability in composite
measures.
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Binding Functions to the Optimization Equations
Table 1 Component Event Binding Table Table 1 Component Event Binding Table Table 1 Component Event Binding Table
Component Types Binding Component Instance Binding Component Event Binding


.
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A Simple Power Function for a Full Platform
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Resolving the Weights for the Power Function
Table 2 Power Function Types, Event Weighting Functions Table 2 Power Function Types, Event Weighting Functions Table 2 Power Function Types, Event Weighting Functions
Function Types Events Weight Functions
Pipeline ibase 6.0
Instruction Types ijmp 2.0
iexcept 2.0
icoproc 12.0
iarith 1.0
Caches (ID) Cache_lookup fi-dcache(size, ways)
icache_hit iCache-lookup ficache(line size, decode)
icache_miss Icache_lookup
dcache_hit Dcache_lookup fdcache(size, ways, line size,)
dcache_miss Dcache_lookup
TLB tlb_miss 30.0
Register regfile_access 1.0
Memory (incl. bus transactions) membus_transaction 50.0
Periph Device (incl. bus transactions) periphbus_reg_access 50.0
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Single Task Working Set vs Cache Size Analysis
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Linux Boot - Memory Hierarchy Analysis (ID
cache bus bus bridge Mem (DDR SDR)
Analysis
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Replace Cache with Simple External Buffer for a
Known Task Set
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The Message

• System optimization needs a composite, complex
  optimization function of functions operating on a
  complete (model of a) system. The constituent
  functions include
• Power
• Speed
• Response deadline compliance
• Cost
• A rigorous scientific methodology is required for
  empirical experimentation