2Write the verilog module for 2 to 4 line decoder'

1
Chapter 4

• (2) Write the verilog module for 2 to 4 line
  decoder.
• (3) Write the verilog module for 3 to 8 line
  decoder.
• (4) Write the verilog module for 4 to 16 line
  decoder.
• (5) Write the verilog module for an 8 bit
  comparator.

(1) Write the Verilog module (program) for the
given AOI gate.
2
Chapter 4 Cont.

• (6) Draw the half-adder circuit in form of Ex-OR
  gates and AND gate.
• Prepare a half-adder module in terms of Ex-OR
  and AND gate primitive.
• (7) Prepare a full-adder module using half-adder
  module and OR gate primitive.
• (8) Prepare a 4 bit adder module in terms of
  full-adder and half-adder modules. Treat the two
  4 bit numbers as vectors for all input
  combination.
• (9) Prepare a module for conversion of an 8 bit
  number into its respective BCDs.
• (10) Prepare a module to add two BCDs.

3
Chapter 4 Cont.

• (11) Prepare a module to generate the 1s
  complement of a 4 bit number.
• (12) Prepare a module to generate the 2s
  complement of a 4 bit number.
• (13) Use the 2 to 4 decoder module and prepare
• (a) a 4 to 1 multiplexer module
• (b) a 1 to 4 demultiplexer module
• (14) Write the verilog desing module for a 2 to 1
  mux module formed with tri-state buffers.