332:578 Deep Submicron VLSI Design Lecture 22 Power Distribution and PhaseLocked Loop Clocking

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332578 Deep SubmicronVLSI Design Lecture
22Power Distribution andPhase-Locked Loop
Clocking

• Mike Bushnell
• Rutgers University
• Spring 2005

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Outline

• Power Distribution
• On-Chip Network
• IR Drops
• Power Supply Droop
• L di/dt
• Bypass Capacitance
• Power Network Modeling
• Return Loops
• Substrate Noise
• Phase-Locked Loop Clocking
• Summary

Material from CMOS VLSI Design,by Weste and
Harris, Addison-Wesley, 2005
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Power Distribution

• Consists of metal wires on the chip, package, and
  board bypass Cs to supply instantaneous
  current
• Properties
• Maintains stable VDD with little noise
• Supplies average and peak power needs
• Provides signal current return paths
• Avoids wearout electromigration and
  self-heating
• Consumes little chip area wiring
• Easy to lay out
• Typical noise goal /- 5 or 10

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Sun mprocessor Power
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On-Chip Network

• Standard cell strapping

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Alternate Strapping
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Large, High-Power Layouts

• Problems
• Resistance of power in thin lower-level metal
• Causes too much IR drop
• Current must be carried on wide, thick
  upper-metal grid
• Grids on middle/lower layers bring current down
  to cells
• Provide ample vias to carry high currents
• When pad ring used, biggest IR drop near chip
  center
• Better solution use C4 solder bumps throughout
  area of chip rely on low-R power plane in
  package

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6-Layer Metal Power Dist.
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X-X Cross Section
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Y-Y Cross Section
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IR Drops

• Power supply network R includes
• R of on-chip wires/vias
• R of bond wires/solder bumps to package
• R of package planes (traces)
• R of printed circuit board (PCB) places
• Package/PCB -- much thicker wider Cu than chip
• ? Chip R dominates IR drop
• IR drop from both average instantaneous power
• Instantaneous (larger) spikes near clock edge
• Use bypass C to supply instantaneous power
• Network needs low R to supply average power

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Power Supply Droop
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L di/dt Noise

• Power supply inductance dominated by
• L of bond wires (1 nH/mm)
• L of controlled collapse chip connection (C4)
  bumps (100 pH)
• L of multiple Ls in parallel is reduced
• ? 50 of package pins are power/ground
• Biggest current transients
• Switching I/O signals
• Changes between idle and active chip core mode
• Cannot transition between min and max power in 1
  clock period
• Pipeline now must enter/exit idle mode 1 stage at
  a time

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On-Chip Bypass Capacitance

• Bypass or decoupling C
• Handles instantaneous chip current demands
• Must be distributed across chip
• Local spike supplied by local bypass C, not by R
  of overall power grid
• Greatly reduces di/dt drawn from package
• Provided by gate C of quiescent transistors
• Called symbiotic bypass C

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Symbiotic Bypass C

• Cgs3 Cgs4
• Usually, ½ of gate C of transistor is symbiotic
• Usually small of gates switching at any time
• ? Nearly ½ of entire chip gate C is symbiotic

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Symbiotic C

• Adequate for low- or medium-power chips
• Inadequate for high-power chips
• Must provide explicit symbiotic C
• Make with nMOSFET with gate at VDD, drain
  source at VSS

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Decoupling C Layout

• Maximize C / area
• Make transistor as long as possible
• Most of area is gate oxide, not contacts
• If too long, transistor R causes too slow a
  response
• Use L 4 to 12 X minimum
• Waffle layout openings in poly let diffusion be
  grounded, use VDD contacts to connect POLY to
  METAL to bump pads
• May leak too much with thinner oxide and
  tunneling
• Will then require specialized oxide layer for
  bypass Cs

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Waffle Bypass C
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May Violate Antenna Rules

• Use circuit to fix this

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Power Network Modeling
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Real Cs

• Has series R and series L and self-resonant f
• Larger Cs have higher series Ls
• Leads to lower self-resonant fs, beyond which
  they are useless
• Use many Cs of different sizes
• Give low Z over all fs of interest

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Impedance of Bypass C

• 1 mF C with 0.25 nH L and 0.03 W R

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Effectiveness of Cs

• Bulk ceramic Cs effective over 1-10 MHz
• Package Cs effective over 10-200 MHz
• Above 200 MHz, L of solder bumps or bond wires
• Makes all but on-chip decoupling Cs ineffective
• Bypass Cs resonate with series L of package
  solder bumps
• Makes low L across all frequencies hard to
  achieve
• Some packages high Z in 10-100 MHz caused by
  resonances
• Below clock f of many chips
• Power supply noise is severe if chip alternates
  between high- and low-power operation at resonant
  f

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Supply Z vs. Frequency

• With multiple resonances

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Need for Bypass Cs

• Sudden current spike in chip
• Delay until spike reaches power supply
• Supply adjusts current it delivers
• Current returns to chip
• Lower delay bound is speed of light
• When gate switches
• Regulator does not know about it until after
  transition
• Current to charge load must come by nearby bypass
  C
• Causes supply drop later recharged by voltage
  regulator, which recharges bypass Cs

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Distributed Power Model

• Needed to model supply voltage variation across
  chip

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Full-Chip Power Grid

• Simulation takes many days to run
• Current signatures of synthesized logic, SRAM,
  repeater banks, and domino logic differ
• Shows map of voltage vs. time for current pattern
• Itanium 2 IR droop greatest in integer execution
  unit
• Several power-hungry domino adders contributed

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Itanium 2 VDD Droop
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Signal Return Paths

• Current flows in loops
• Signal sent down wire
• Current must return to driver through VDD/VSS
  wires
• Power supply network is signal return path
• Impedance between VDD and VSS is low at high f
• Due to decoupling Cs
• High f AC current flows readily between VDD VSS
• Both can be signal return paths for both 0 and
  1

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Signal Return Paths

• L of wire a current loop area
• Large L increases delay or causes noise
• ? Good power network must provide return paths
  near all signal paths
• Keep current loop area small
• Signals with overlapping loop areas have mutual L

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Long Signal Return Paths

• Causes pathological behavior

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Solution

• Wire speed of light set by
• Power grid should occupy 2 or more orthogonal
  metal layers
• Do not use fingers on 1 metal layer
• Put 1 VDD or GND line for each N signal lines on
  each metal layer
• Use signal-to-return (SR) ratio of N 10 on at
  least 2 orthogonal upper metal layers
• Ensures that no path has long return paths
• Use SR of 21 at high f
• Every signal has VDD or GND as a neighbor
• Reduces capacitive crosstalk 2 X

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Power Supply Filtering

• Circuits particularly sensitive to power noise
• Phase-locked loop (PLL)
• Clock buffers causes clock jitter
• Analog circuits
• Pentium 4 power supply filter
• On clock buffers to reduce jitter
• Attenuates supply noise from 10 to 2 of VDD
• Uses pMOSFET as R
• RC time constant of 2.5ns
• IR drop of 70 mV

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Power Supply Filtering

• Eliminates high-f noise on power supply

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Substrate Noise

• Current flow in substrate causes noise on
  transistor body terminal
• C Coupling through reverse-biased source/drain to
  substrate diodes
• Impact ionization as I flows through ON
  transistor
• Substrate noise modulates Vt by body effect
• Mixed-signal designs
• Large of rapidly-switching digital gates inject
  noise on digital VSS that enters analog circuit
  via common substrate

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Substrate Noise Fixes

• Use plenty of substrate/well contacts, spaced
  throughout substrate/well area
• Separate analog circuits from digital
• Surround analog circuits with guard rings
• Some processes have much less substrate coupling
  since transistors are isolated in their own wells
• Twin-tub
• Triple-well
• Silicon-on-Insulator (SOI)

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Types of Clocking Systems

• Single Phase
• Double Phase

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Clock Design Guidelines

• Period when charge stays on storage C governed
  by source/drain leakage, depends on T
• Always refresh or clamp dynamic modes when in
  standby or low-power mode
• Use phased-locked loop
• To synchronize internal external clocks (in
  phase)
• To operate internal clock faster than external
  clock (clock doubling, tripling, or quadrupling)

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Ordinary Clock
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Phase-Locked Loop Clocks
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Clock Multiplying PLL
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PLL Synchronizer
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Summary

• Power Distribution
• On-Chip Network
• IR Drops
• Power Supply Droop
• L di/dt
• Bypass Capacitance
• Power Network Modeling
• Return Loops
• Substrate Noise
• Phase-Locked Loop Clocking