Embedded test tutorial

1
Summary
Summary
of embedded test
of embedded test
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ATPG - test pattern generation process
1. Target faults
2. Generate test cube 1-5
3. Random fill 99-95
4. Stimuli on ATE
5. Response on ATE
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Scan/ATPG - non-embedded solution
ATE stimuli
ATE reference
The same width
The same frequency
Mirror images ATE and scan
4
ATPG - the bandwidth problem

• Deterministic
• High fault coverage
• Arbitrary fault models
• Minimal number of
• patterns

• Non-Embedded
• Simplicity
• - Limited number of
• scan chains
• - Limited bandwidth

5
Logic BIST
100
Fault coverage

• BIST-ready core requirement
• Random pattern testable
• X-free responses

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Logic BIST

• Generators
• Pseudorandom - PRPG
• Biased
• Smart
• Deterministic

E q u a l i z e r

P R P G
M I S R
Control

• Test data eliminated completely
• Deigned for board and system test

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Logic BIST

• Pseudorandom
• No stored patterns
• - Lower coverage
• - More patterns
• - BIST-ready design

• Embedded
• - More complex
• Unlimited number
• of scan chains
• Short scan load time

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EDT - Embedded Deterministic Test

• Standard scan
• On-chip continuous flow decompressor
• On-chip continuous flow selective compactor
• Highly compressed deterministic patterns

D E C OMPRESSOR
C OMPA C TOR
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Embedded and deterministic test

• Deterministic
• High fault coverage
• Arbitrary fault models
• Minimal number of
• patterns

• Embedded
• - More complex
• Unlimited number
• of scan chains
• Short scan load time

• Embedded
• Simple
• Unlimited number
• of scan chains
• Short scan load time

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ATPG cycles, coverage, and volume
100
ATPG coverage
80
ATPG volume
60
40
20
0
Cycles
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LBIST cycles, coverage, and volume
100
ATPG top-up coverage
BIST coverage
80
60
40
ATPG top-up volume
20
0
Cycles
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EDT 10X cycles, volume, and energy
100
80
60
40
20
0
Cycles
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Radar View of DFT Technologies
Reference
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ATPG
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ATPG, Logic BIST
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Logic BIST ATPG top up patterns
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EDT
4
6
8
10
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Logic BIST summary

• Logic BIST is ideally suited for applications
  where stored patterns are prohibitive, i.e.
  system test
• Test coverage objectives are achieved by
  pseudorandom patterns and test points
• Unknown states have to be eliminated to allow
  signature based compaction
• For manufacturing test ATPG top up patterns are
  required to achieve the desirable test quality
• For very long test experiments some un-modeled
  defects can be detected

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EDT summary

• EDT is designed for optimized manufacturing test
• Based on standard scan
• No test point are required
• Handles unknown states
• Supports effectively variety of fault models,
  including path delay faults
• Uses tester to execute the test

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Deterministic forms of embedded test

• Designed for optimized manufacturing test
• Tester controls test application
• Very similar flow to scan/ATPG
• Based on standard scan
• Supports the same fault models as ATPG
• No test points necessary
• No bounding of X states necessary (in EDT)
• On-chip hardware facilitates the improved
  efficiency
• Compression of volume of scan test data
• Reduction of scan test time

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Appendices
Appendices
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Acknowledgements

• Alfred Crouch, Motorola
• Graham Hetherington, Texas Instruments
• Mark Croft, Mentor Graphics
• Geir Eide, Teseda
• Rudy Garcia, NP Test
• Abu Hassan, Mentor Graphics
• Mark Kassab, Mentor Graphics
• Nilanjan Mukherjee, Mentor Graphics
• Jun Qian, CISCO
• Nagesh Tamarapalli, Mentor Graphics
• Robert Thompson, Magma DA
• Janice Lawson Richards , Mentor Graphics

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References and sources

• Conference proceedings and tutorial material
• International Test Conference
• Design Automation Conference
• Design and Test in Europe Conference
• VLSI Test Symposium
• Workshops
• Testing Embedded Core-based Systems
• Memory Technology, Design and Testing
• DFT and BIST Workshops
• Test Synthesis Workshop

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References and sources

• Magazines and journals
• IEEE Design and Test of Computers
• IBM Journal of Research and Development
• ATT Technical Journal
• IEEE Transactions on CAD of ICS
• IEEE Transactions on Computers
• Journal of Electronic Testing (JETTA)
• Books
• Abramovici et al., Digital System Testing and
  Testable Design, Computer Science Press, 1990
• Bardel et al., Built-In Test for VLSI, Wiley,
  1987

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References and sources

• Books
• Van der Goor, Testing Semiconductor Memories
  Theory and Practice, John Wiley and Sons, 1991
• Alfred Crouch, Design-For-Test for Digital ICs
  and Embedded Core Systems, Prentice Hall, 1999
• Janusz Rajski and Jerzy Tyszer, Arithmetic
  Built-In Self Test for Embedded Systems,
  Prentice Hall, 1998
• Commercial EDA reference manuals and web pages
• ASIC vendors reference manuals and web pages
• Patent descriptions and US Patent and Trademark
  Office web site

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