The Verilog Hardware Description Language

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332437 Lecture 8Verilog and Finite State
Machines

• Finite State Machines
• Discrete Time Simulation
• Gate Level Modeling
• Delays
• Summary

Material from The Verilog Hardware Description
Language, By Thomas and Moorby, Kluwer Academic
Publishers
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Finite State Machines Review

• In the abstract, an FSM can be defined by
• A set of states or actions that the system will
  perform
• The inputs to the FSM that will cause a sequence
  to occur
• The outputs that the states (and possibly, the
  inputs) produce
• There are also two special inputs
• A clock event, sometimes called the sequencing
  event, that causes the FSM to go from one state
  to the next
• A reset event, that causes the FSM to go to a
  known state

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FSM Review

• The traditional FSM diagram
• We looked at State Transition Diagrams (and
  Tables) last time
• and ended up with a diagram that looked like
  this

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Verilog for the D Flip-Flop
Note that it doesnt matter what the current
state (Q) is. The new state after the clock event
will be the value on the D input.
module DFF (output reg q, input d, clk,
reset) always _at_(posedge clk or negedge
reset) if (reset) q lt 0 else q lt
d endmodule
The change in q is synchronized to the clk
input. The reset is an asynchronous reset (q
doesnt wait for the clk to change).
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Clock Events on Other Planets

• Trigger alternatives
• For flip flops, the clock event can either be a
  positive or negative edge
• Both have same next-state table

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Moore Machine 111 Detector

• Note how the reset is connected
• Reset will make both of the FFs zero, thus
  putting them into state A.
• Most FFs have both reset and preset inputs
  (preset sets the FF to one).
• The reset connections (to FF reset and preset)
  are determined by the state assignment of the
  reset state.

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Verilog Organization for FSM

• Two always blocks
• One for the combinational logic next state and
  output logic
• One for the state register

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Verilog Behavioral Specification
module FSM (x, z, clk, reset) input clk,
reset, x output z reg 12 q,
d reg z endmodule

• Things to note
• reg 12 matches numbering in state
  assignment (Q2 is least significant bit in
  counting)
• lt vs.

always _at_(posedge clk or negedge reset) if
(reset) q lt 0 else q lt d
The sequential part (the D flip flop)
The combinational logic part next state output
always _at_(x or q) begin d1 q1 x
q2 x d2 q1 x q2 x z
q1 q2 end
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Processes Without Sensitivity List or wait
Statement

• Run forever example
• always
• begin
• x lt a and b and c
• end

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Synopsys Deletes All Useless Hardware from Your
Design

• Synthesis Since x can never be other than 0,
  hardwire x to 0
• Moral
• Signals are not updated until end of process even
  if they change in the middle of it due to lt
  operator
• Expressions based on current value of signals on
  RHS of lt symbol
• Signals updated with value in last assignment
  statement in process
• Order of concurrent signal assignment statements
  is of no consequence

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Benefit of Dont Cares

• Dont care condition produces less hardware
• y lt s1 s0
• Rather than
• y lt s1 s0 s1 s0

s1
s0
s1
s0
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Verilog Overview

• Verilog is a concurrent language
• Aimed at modeling hardware optimized for it!
• Typical of hardware description languages (HDLs),
  it
• Controls time
• Provides for the specification of concurrent
  activities
• Stands on its head to make the activities look
  like they happened at the same time Why?
• Allows for intricate timing specifications Why?
• A concurrent language allows for
• Multiple concurrent elements
• An event in one element to cause activity in
  another. (An event is an output or state change
  at a given time)
• Based on interconnection of the elements ports
• Logical concurrency software
• True physical concurrency e.g., lt in Verilog

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Discrete Time Simulation

• Discrete Time Simulation
• Models evaluated and state updated only at time
  intervals n?
• Even if there is no change on an input
• Even if there is no state to be changed
• Need to execute at finest time granularity
• Might think of this as cycle accurate things
  only happen _at_(posedge clock)
• You could do logic circuits this way, but either
  
• Lots of gate detail lost as with cycle accurate
  above (no gates!)
• Lots of simulation where nothing happens every
  gate is executed whether an input changes or not.
  
• Discrete Event Simulation
• Picks up simulation efficiency due to its
  selective evaluation
• Only execute models when inputs change

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Discrete Event (DE) Simulation

• Discrete Event Simulation
• Events changes in state at discrete times.
  These cause other events to occur
• Only execute something when an event has occurred
  at its input
• Events are maintained in time order
• Time advances in discrete steps when all events
  for a given time have been processed
• Quick example
• Gate A changes its output.
• Only then will B and C execute
• Observations
• The elements in the diagram dont need to be
  logic gates
• DE simulation works because there is a sparseness
  to gate execution maybe only 12 of gates
  change at any one time.
• The overhead of the event list pays off then.

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Observations

• Hmm
• Implicit model execution of fanout elements
• Implicit?
• Concurrency is it guaranteed? How?
• Time a fundamental thingie
• Cant you represent this all in C? After all,
  the simulator is written in it!
• Or assembly language?
• Whats the issue?
• Or how about Java? Ya-know, arent objects like
  things you instantiate just like in Verilog?
• Cant A call the port-2 update method on object B
  to make a change?

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A Gate Level Model

• A Verilog description of an SR latch
• module nandLatch
• (output q, qBar,
• input set, reset)
• nand 2
• g1 (q, qBar, set),
• g2 (qBar, q, reset)
• endmodule

A module is defined
name of the module
Draw the circuit
The module has ports that are typed
type and delay of primitive gates
primitive gates with names and interconnections
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A Gate Level Model

• Things to note
• It doesnt appear executable no for loops,
  if-then-else, etc.
• Its not in a programming language sense, rather
  it describes the interconnection of elements
• A new module made up of other modules (gates) has
  been defined
• Software engineering aspect we can hide detail
• module nandLatch
• (output q, qBar,
• input set, rese)t
• nand 2
• g1 (q, qBar, set),
• g2 (qBar, q, reset)
• endmodule

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Kinds of Delays

• Transport delay
• Input to output delay (sometimes propagation)
• Zero delay models (all transport delays 0)
• Functional testing
• Theres no delay, not cool for circuits with
  feedback!
• Unit delay models (all transport delays 1)
• All gates have delay 1. OK for feedback
• Edge sensitive delay is value sensitive

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Some More Gate Level Examples

• An adder
• module adder
• (output carryOut, sum,
• input aInput, bInput, carryIn)
• xor (sum, aInput, bInput, carryIn)
• or (carryOut, ab, bc, ac)
• and (ab, aInput, bInput),
• (bc, bInput, carryIn),
• (ac, aInput, carryIn)
• endmodule

instance names and delays optional
ab
bc
ac
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Adder With Delays

• An adder with delays
• module adder
• (output carryOut, sum,
• input aInput, bInput, carryIn)
• xor (3, 5) (sum, aInput, bInput, carryIn)
• or 2 (carryOut, ab, bc, ac)
• and (3, 2) (ab, aInput, bInput),
• (bc, bInput, carryIn),
• (ac, aInput, carryIn)
• endmodule

each AND gate instance has the same delay
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Adder, Continuous Assign

• Using continuous assignment
• Continuous assignment allows you to specify
  combinational logic in equation form
• Anytime an input (value on the right-hand side)
  changes, the simulator re-evaluates the output
• No gate structure is implied logic synthesis
  can design it.
• The description is more abstract
• A behavioral function may be called details
  later
• module adder
• (output carryOut, sum,
• input aInput, bInput, carryIn)
• assign sum aInput bInput carryIn,
• carryOut (aInput bInput) (bInput
  carryIn)
• (aInput carryIn)
• endmodule

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Im Sick of This Adder

• Continuous assignment assigns continuously
• Delays can be specified (same format as for
  gates) on whole equation
• No instances names nothing is being
  instantiated.
• Given the same delays in this and the gate-level
  model of an adder, there is no functional
  difference between the models
• FYI, the gate-level model gives names to gate
  instances, allowing back annotation of times.
• module adder
• (output carryOut, sum,
• input aInput, bInput, carryIn)
• assign (3, 5) sum aInput bInput
  carryIn
• assign (4, 8) carryOut (aInput bInput)
  (bInput carryIn) (aInput carryIn)
• endmodule

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Summary

• Finite State Machines
• Discrete Time Simulation
• Gate Level Modeling
• Delays
• Summary