Onchip MRAM as a HighBandwidth, LowLatency Replacement for DRAM Physical Memories

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On-chip MRAM as a High-Bandwidth, Low-Latency
Replacement for DRAM Physical Memories

• Rajagopalan Desikan, Charles R. Lefurgy,
• Stephen W. Keckler, and Doug Burger
• Computer Architecture and Technology Lab
• University of Texas at Austin

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Motivation

• Latency to off-chip memory hundreds of cycles
• Off-chip memory bandwidth becoming a performance
  limiting factor
• MRAM Emerging memory technology with high
  bandwidth and low latency
• Goal of our work - To determine if the
  performance advantage of MRAM in high performance
  computing is worth more investment and research

MRAM has the potential to provide low latency,
high bandwidth
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Outline

• MRAM Memory Description
• MRAM Memory Hierarchy
• Results
• Conclusions

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MRAM Cell

• Magnetoresistive random access memory (MRAM) uses
  the magnetic tunnel junction (MTJ) to store
  information
• MRAM cell composed of a diode and an MTJ stack
• MTJ stack consists of two ferromagnetic layers
  separated by a thin dielectric barrier
• Polarization of one layer fixed, other used for
  information storage

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MRAM Bank Design

• MRAM cells located at the intersection of each
  word and bit line
• Read Connect current sources to bit lines and
  selected wordline is pulled low
• Writes Polarity of current in the bit lines
  decides value stored
• MRAM banks accessed using vias

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MRAM Bank Modeling

• Modified CACTI-3.0 to develop an area and timing
  tool to model MRAM banks
• Independently accessible composed of sub-banks
• Important features
• Active area consumed
• Delay due to vertical wires
• MRAM capacity for a given die size and cell size
• Support for multiple layers with sharing
• SIA 2001 roadmap at 90 nm technology

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Chip-Level Architecture
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MRAM Design Issues

• Number of Banks
• More banks Low latency, higher concurrency,
  higher network traversal time, higher miss rates
• Cache Line Size
• Larger line size More spatial locality, higher
  latency
• Page Placement Policy
• Random
• Round-robin
• Least loaded

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Methodology

• Simulated Processor
• Alpha 21264 pipeline modified for 8 wide issue
• 3.8 GHz (10 FO4 inverters per stage)
• Base SDRAM System
• Distributed L2 cache
• Base MRAM system
• Distributed MRAM banks and reduced capacity
  distributed L2 cache
• Benchmarks
• Memory intensive SPEC CPU2000, Scientific, Speech

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Page Placement Policy
IPC for 100 banks with different page placement
policies
CostLeast-Loaded (L2 Hit Rate L2 Hit
Latency) (L2 Miss Rate MRAM Bank
Latency) Current Network Latency to Bank
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MRAM Sensitivity
20
40
60
30
MRAM Latency Sensitivity
SDRAM Latency 30 ns
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Conclusions

• Developed an architectural model for exploiting
  an emerging memory technology, MRAM
• Analyzed the contribution to performance of the
  different components in our MRAM system
• MRAM system performs 15 than conventional SDRAM