EEL 5722 FPGA Design Fall 2003 SelfTimed FPGAs Part I

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EEL 5722FPGA DesignFall 2003Self-Timed
FPGAsPart I
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Asynchronous vs. Synchronous Circuits
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Asynchronous vs. Synchronous Circuits
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Advantages of Asynchronous Circuits(Al Davis,
Asynch 94)
Asynchronous circuits (AC) achieve average case
performance by exploiting data dependencies. ACs
perform better if the difference between the
average and worst case is large. Care must be
taken not to spend excessive time in computation
completion detection.
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Power Consumption of ACs(Al Davis, Asynch 94)
ACs consume power only when needed on-demand
power consumption. CMOS implementations of ACs
consume power only during transitions. ACs
eliminate the clock which performs countless
transitions.
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Power Consumption of ACs(Al Davis, Asynch 94)
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Modular Composition of ACs(Al Davis, Asynch 94)
The design of ACs lends itself to modular
composition (building by blocks). This design
process allows also incremental
improvements. Building by blocks can be modeled
by using an object-oriented design approach for
hardware.
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Absence of Clocked Interfaces(Al Davis, Asynch
94)
ACs do not require clock alignment at subsystem
interfaces. Indeed, the synchronization of an
incoming signal to a clock requires great care
and is time consuming. By using ACs,
metastability can be prevented to a large
extent. Without a clock, ACs can adapt naturally
to a variety of data rates.
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Clock Distribution(Al Davis, Asynch 94)
Without a clock, ACs can avoid clock distribution
problems. Clock distribution problems are a
major drain on design time and power budgets. In
addition, clock lines tend to consume a large
chip area.
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Global Synchrony(Al Davis, Asynch 94)
Some state that global synchrony does not exist
anyway. It is only a useful abstraction, not
reality. With increased density and chip area,
the problems of clock distribution and clock
speed prevent a design from having a single
global clock. Furthermore, these problems are
exacerbated by the requirement of heterogeneous
timing for new chips. As a result, new directions
are being explored to overcome these problems
such as Globally Asynchronous Locally Synchronous
(GALS) approach.
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Concurrency in ACs(Al Davis, Asynch 94)
ACs offer a natural way to exploit
concurrency. Concurrency in AC design happen
naturally instead of supporting it through
interleaved execution.
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Low Noise and Low Emission
A digital circuit can emit electromagnetic
radiation at its clock frequency. A neighboring
radio receiver circuit may mistake this radiation
for a radio signal. Due to the absence of a
clock, ACs may have better noise and
electromagnetic properties than synchronous
circuits.
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Low Noise and Low Emission
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Timing Models of ACs
A circuit is modeled as a closed network of
gates. A closed network is a network in which
all inputs are connected to outputs and
vice-versa. The state of the circuit is the set
of all gate outputs.
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Speed-Independent (SI) ACs
A speed-independent (SI) circuit is a circuit
that operates correctly assuming positive,
bounded but unknown delays in gates and ideal
zero-delay in wires. Assuming zero-delay in
wires is not realistic in todays CMOS processes.
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Delay-Insensitive (DI) ACs
A delay-insensitive (DI) circuit is a circuit
that operates correctly assuming positive,
bounded but unknown delays in gates and
wires. Although these circuits can be quite
robust, their number is very small.
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Quasi Delay-Insensitive (QDI) ACs
A quasi delay-insensitive (QDI) circuit is a DI
circuit with isochronic forks. An isochronic
fork is a wire fork whose wire delays on both
wire branches of the fork are identical. In
practice, these forks are implemented in the gate
implementations of basic building blocks.
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Data Signaling Protocols of ACs
The bundled-data protocol refers to a situation
where the data signals use normal Boolean levels
to encode information, and where separate request
and acknowledge wires are bundled with the data
signals. Bundled-data protocols are also
called single-rail encoding.
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Dual-Rail Data Signaling
The dual-rail protocol uses two wires to
represent one bit, but the information is encoded
as transitions or events.
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Control Signaling in ACs
The most basic control protocol is the
Request/Acknowledge protocol. This protocol can
be layered on top of data signaling protocol.
The sender issues a Request to the receiver
before sending the data. The receiver replies by
sending an Acknowledge to the sender. Then the
sender sends the data. If the sender initiates
the data transfer, the transfer channel is a
push-channel. On the other hand if the receiver
initiates the transfer, the channel is a
pull-channel.
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The Four-Phase Protocol

• The four-phase protocol refers to the number of
  communication actions
• The sender issues data and sets Req to high
• (ii) The receiver absorbs the data and sets Ack
  to high
• (iii) The sender responds by setting Req to low
• (iv) The receiver acknowledges by setting Ack to
  low
• This protocol can be used with both single and
  dual-rail encoding.

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The Four-Phase Protocol
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The Two-Phase Protocol
The two-phase protocol follows these steps (i)
The sender sends data and produces a Req
event (ii) The receiver absorbs data and produces
an Ack event In some cycles, an event can be a
rising transition and in some it can be a falling
transition. There is no difference between
them. The three events, data change, request
event, and acknowledge event always follow in
cyclic order. Successive cycles may take
different amounts of time. This protocol
eliminates the superfluous return-to-zero transiti
ons in the four-phase protocol.
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The Two-Phase Protocol
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Circuit Implementation Styles
Four-phase bundled-data which most closely
resembles the design of synchronous circuits and
which normally leads to the most efficient
circuits, due to the extensive use of timing
assumptions (example Amulet 2 processor).
Two-phase bundled-data known also as
micropipelines and introduced by Ivan Sutherland
in his 1988 Turing Award lecture (example Amulet
1 processor) Four-phase dual-rail the
classic approach introduced by Mullers
pioneering work in the 1950s. Two-phase
dual-rail such as Level-Encoded two-phase
Dual-Rail scheme (LEDR).