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EVM Project Status

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M. Litmaath, TriDAS Review Nov. 6-10, 2000. 3. EVM Test Bench Updates ... M. Litmaath, TriDAS Review Nov. 6-10, 2000. 5. EVM Software on XDAQ. XDAQ BM modified: ... – PowerPoint PPT presentation

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Title: EVM Project Status


1
EVM Project Status
  • People
  • S. Aziz
  • M. Litmaath
  • C. Moore
  • V. ODell
  • S. Pavlon
  • K. Sumorok
  • I. Suzuki
  • Institutes
  • FNAL
  • MIT

2
Contents
  • Test bench hardware
  • IEEE1394 benchmark test
  • BM software in XDAQ
  • Simulation
  • Plans

3
EVM Test Bench Updates
  • Four additional nodes (18 in total)
  • Myrinet (PCI64A), 100 Mbps Ethernet (public
    private), IEEE1394
  • VME PowerPC board MVME2300
  • RM, IEEE1394 bus fan-out board development
  • S. Aziz (50 ) joined the project

UP
PPC
FastEthernet
IEEE1394
SMP
Myrinet
4
IEEE1394 Benchmark (S.Pavlon)
  • Linux 2.2.14 kernel beta driver 20000616
  • D-Link IEEE1394 PCI I/F (400 Mbps)
  • Asynchronous write
  • Latency 53 µs
  • Bandwidth 34 MB/s

5
EVM Software on XDAQ
  • XDAQ BM modified
  • stores EventID in object shared by BM and RM
  • EventID lifetime
  • number of allocated EventIDs
  • etc.
  • keeps statistical info in ROOT
  • histograms and n-tuples
  • BM worked on FNAL test bench and CERN machines
  • RM code under development
  • original XDAQ RM was used in tests

6
XDAQ Benchmark at FNAL
  • Configuration
  • One unit (EVM/RU/BU) driven by one XDAQ executive
    on each machine
  • Block size 4 kB, request 20, 10 msg/packet
  • Event throughput
  • 1 to 1 0.5 kHz _at_ EVM, 1.85 MB/s _at_ BU
  • 1 to 2 1.0 1.85
  • 1 to 3 1.8 1.85
  • 2 to 1 0.5 3.72
  • 2 to 2 1.0 3.72
  • 3 to 1 0.5 5.58

7
XDAQ Benchmark at FNAL (cont.)
  • 1 to 1 20 events active in the system
  • Event throughput proportional to BUs
  • Transfer rate behaves strangely
  • Bandwidth sometimes twice higher in first 10
    seconds
  • 1 to 3 BUs do not receive events evenly
  • Further study needed
  • Statistical information in the BU may help

8
EVM Simulation
  • EVBSIM new components
  • BCN using BCNICs
  • BDN using BDNICs
  • NICs ensure each endpoint does only one
    send/receive at a time
  • currently BCNIC can send and receive at the same
    time (easy to change)
  • Problems
  • 500x500 cannot keep up with trigger rate
  • RU does not implement barrel shifter not trivial
  • BU traffic shaping may be the solution
  • 500x500 memory usage gt 2 GB !

9
EVBSIM Modules
The given numbers are typical for LHC operation.
10
NxN Test Stand Setup
  • 100 Mbps single private Ethernet
  • Latency 72 us, BW 9.6 MB/s TCP
  • Used for BCN and BDN
  • EVBSIM uses 2 networks
  • Not a problem here
  • 1x1 and 2x2 test cases
  • 0.0 ms L2, using all RUs
  • Trigger rates
  • Observed in XDAQ
  • Input for EVBSIM
  • 0.5 kHz 1x1, 1.0 kHz 2x2
  • 1 BCN packet of 160 B per 10 ev.
  • 1 BDN packet of 2 kB per 1 event
  • Expected latencies
  • 3 (3 1 in parallel) BCN and 10 (20) BDN
    messages per batch
  • 1x1 3 (72 160/9.6) 10 (72 2048/9.6)
    3119 us
  • 2x2 3 (72 160/9.6) 20 (72 2048/9.6)
    5973 us

11
NxN Test Stand Comparison
  • XDAQ

EventID
1 to 1
2 to 2
lifetime
EVBSIM
12
EVM Plans
  • EVM SW development on XDAQ
  • RCN SW development benchmark
  • IEEE1394 evaluation
  • Understand test stand latencies
  • Discuss how to proceed with EVBSIM
  • Implement BU traffic shaping
  • Compare with test stand anyway
  • Run control for XDAQ (C. Moore)
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