DSP Processor Architectures

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DSP Processor Architectures
Presented by Saroj Kumar Panda 2003EEZ0019
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DSP Applications
Digital audio applications MPEG Audio
Portable audio Digital cameras Cellular
telephones Wearable medical appliances
Storage products disk drive servo control
Industrial control Networking Wireless
Base station Cable modems Military
applications radar sonar
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TYPES OF DSP PROCESSORS 32-BIT FLOATING POINT
(5 of market) TI TMS320C3X, TMS320C67xx
ATT DSP32C ANALOG DEVICES ADSP21xxx
Hitachi SH-4 16-BIT FIXED POINT (95 of
market) TI TMS320C2X, TMS320C62xx Infineon
TC1xxx (TriCore1) MOTOROLA DSP568xx,
MSC810x ANALOG DEVICES ADSP21xx Agere
Systems DSP16xxx, Starpro2000 LSI Logic
LSI140x (ZPS400) Hitachi SH3-DSP StarCore
SC110, SC140
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Basic Architectural Features of DSPs
Data path configured for DSP Fixed-point
arithmetic MAC- Multiply-accumulate Multiple
memory banks and buses - Harvard
Architecture Multiple data memories
Specialized addressing modes Bit-reversed
addressing Circular buffers Specialized
instruction set and execution control Support
for fast MAC Fast Interrupt Handling
Specialized peripherals for DSP
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Basic Features of DSPs
DSP processors are microprocessors designed for
efficient mathematical manipulation of digital
signals. DSP in-sensitive to environment DSP
performance identical even with variations in
components analog systems behavior varies even
if built with same components with 1 variation
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Basic Features of DSPs
DSPs tend to run one program, not many
programs. Hence OSes are much simpler, there
is no virtual memory or protection, ... DSPs
usually run applications with hard real-time
constraints DSPs usually process infinite
continuous data streams. The design of DSP
architectures and ISAs driven by the requirements
of DSP algorithms.
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Basic Features of DSPs
The algorithms of DSPs Inifinite Impule
Response (IIR) filters Finite Impule Response
(FIR) filters FFT, and convolvers In
DSPs, target algorithms are important Binary
compatibility not a mojor issue High-level
Software is not (yet) very important in DSPs.
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Architecture of the Digital Signal Processor
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Architecture of the Digital Signal Processor
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Programmable and Application-specific DSP
processors
Systems with programmable processors are called
multiprocessor system
Systems with application-specific processors are
called array system

• Array processors should have the following
  characteristics
• Synchrony
• Regularity and modularity
• Spatial and temporal locality
• Parallelism and Pipelinability

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Programmable Digital Signal Processors
Design Process for Array Processors
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Programmable Digital Signal Processors
Systolic Architecture
100ns 5 MOPS AT MOST The conventional
processor
100ns 30 MOPS AT MOST A systolic
processor array
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Systolic Architecture
Programmable Digital Signal Processors

• Characteristics
• Each data item can be used and re-used before
  the final result reaches the memory.
• Several data items can be processed concurrently.
• The operations performed by the processors at
  each step are simple.
• The architecture has a regular geometry, and the
  flow of control and data is regular and
  consistent across the processors.
• The regular and localized communication geometry
  reduces routing costs, power, time and chip area
  required to implement a computation

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CORDIC Architecture

• The basic of the algorithm is the coordinate
  rotation in a linear, circular or hyperbolic
  coordinate system depending on which function is
  to be calculated iteratively with simple shift
  and add operations
• By varying a few simple parameters, the same
  CORDIC processor is capable of iteratively
  evaluating this elementary function using the
  same hardware within same amount of time.
• The CORDIC algorithm can also be implemented with
  VLSI to achieve high throughput computation in
  real time signal processing

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Programmable Digital Signal Processors
Data Path Synthesis

• This is used to designate the transformation of
  a behavioral description to a structural
  representation.
• Its aim is to determine a suitable hardware
  structure as automatically as possible from a
  behavioral description.
• Data path synthesis allows systematic derivation
  of the structure of a data path to be
  synthesized.

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Programmable Digital Signal Processors
Data Path Synthesis
Starting from a CDFG, the data path synthesis
comprises three major subtasks

• Scheduling
• Assigning operations to time or control steps,
  taking into consideration the dependences between
  operations

(2) Allocation Selection of functional and
storage units
(3) Binding Binding of units
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Programmable Digital Signal Processors
Scheduling and allocation for simple CDFG
S3 X0 x W0 X1 x W1 X2 x W2
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Programmable Digital Signal Processors
DIF Array Processors for one-dimensional DHT
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Programmable Digital Signal Processors
DIF Array Processors for one-dimensional DHT
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Programmable Digital Signal Processors
DIT Array Processors for one-dimensional DHT
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References

• Architectures for Digital Signal Processing by
  Peter Pirsch WILEY
• The Scientist and Engineers Guide to Digital
  Signal Processing www.ti.com
• W.H. Fang and J.D.Lee,Efficent CORDIC-based
  systolic architectures for the DHT,IEEE Proc.,
  Comput. Digit. Tect., Vol.142,pp201-207, May 1995
• www.bdti.com