Edge-triggering

1
Edge-triggering
In a positive edge-triggered D Flip-Flop, the
output looks at the input only during the instant
that the clock changes from low to high.
The carrotsymbol meansedge-triggered
Edge-triggered D Flip-flop Every rising edge,
output is set to the input
2
Negative Edge-triggering
In a negative edge-triggered D Flip-Flop, the
output looks at the input only on the falling
edge of the clock.
Negative Edge-triggered D Flip-flop Every
falling edge, output is set to the input
3
Triggering on an Edge
We want to briefly enable the FlipFlop whenever
we find a rising edge
Edge detection using the time delay through an
inverter
In reality, this will be delayed by the AND gate
4
D Latch and FF states
Level-sensitive (gated) D-latch
Edge-triggered D-FF
Edge-triggered D-FF with clock omitted
5
VHDL for D FlipFlops
LIBRARY ieeeUSE ieee.std_logic_1164.allENTITY
DFF IS PORT( D IN STD_LOGIC CLK IN
STD_LOGIC Q INOUT STD_LOGIC) END DFF
Inputs D and CLKOutput Q
PROCESS list ? State of latch can change due to a
change in any of these values
ARCHITECTURE behavior OF DFF ISBEGIN PROCESS(CLK
) BEGIN IF RISING_EDGE(CLK)THEN Q lt D
END IF END PROCESS END behavior
Continuously monitors CLK, but not D (Q only
changes on CLK edge)
Wait until the clock has a rising edge
Q only changes on rising edge
6
J-K Flip-Flops
We want to eliminate the forbidden state of the
R-S Latch (when R and S are both 1).Idea Q, Q
are always different. Use them to control the
input.
J, K act just like Set and Reset, except When
theyre both 1, we get a toggle.
7
VHDL for J-K FlipFlops
LIBRARY ieeeUSE ieee.std_logic_1164.allENTITY
JKFF IS PORT( J,K IN STD_LOGIC CLK IN
STD_LOGIC Q INOUT STD_LOGIC
QB OUT STD_LOGIC) END JKFF
Inputs J,K and CLKOutput Q and Q
ARCHITECTURE behavior OF JKFF ISBEGIN PROCESS(CL
K) BEGIN IF RISING_EDGE(CLK)THEN IF
(J1 AND K0) THEN Q lt1 ELSIF
(K1 AND J0) THEN Q lt0 ELSIF (J1
AND K1) THEN Q lt NOT(Q) ELSE
Q lt Q END IF END
IF QB lt NOT(Q) END PROCESS END behavior
Continuously monitors CLK, but not J or K (Q only
changes on CLK edge)
On clock edge, define outputs for all possible
inputs
8
Toggle Flip-Flops
Build a flip-flop that toggles its state on each
clock edge whenit is enabled (T is the enable).
Q is the Q output after the clock changes
9
Asynchronous Presets and Clears
Clear forces the output low regardless of the
other inputs. Preset forces the output high
regardless of the other inputs.
Ordinary level-sensitive D-latch
Clear - Force S0, R1
Preset - Force S1, R0
Asynchronous - doesnt matter whether clock is
high or low
10
Racing the clock
Real signals dont change instantly
D is changing during the rising edge of Clk. Is a
1 or 0 clocked in?
D is changing right after the rising edge of Clk.
Is a 1 or 0 clocked in?
11
Setup and Hold Times
Setup Time How long a signal must be stable
preceding the clock edge
Hold Time How long a signal must be stable after
the clock edge
Clk
D
Setup PassHold Pass
Setup FailHold Pass
Setup PassHold Fail
Setup Fail Hold Fail
12
Setup and Hold times Flip Flops
74LS74 PositiveEdge TriggeredD Flipflop
Setup time 20ns Hold time
5ns  Propagation delays - Low to High 23
ns max, 13 ns typ - High to Low 40 ns max,
25 ns typ