MPC555 Onchip IO and Interrupt System

1
MPC555 On-chip I/O and Interrupt System

• Part II MPC555 Internal I/O Modules, Hardware
  interconnects, Interrupt Controller, External
  Interrupt ESR

2
External Interrupt ESR

• Two major aspects
• Exception processing Interrupt and resume
  programming execution
• Interrupt processing Read interrupt registers,
  find and call ISR

3
External Interrupt ESR

• General procedures
• Save machine contexts
• Re-enable interrupts
• Save user-level registers
• Read interrupt vector code
• Calculate ISR address and jump to ISR
• Restore machine contexts and user-level registers
• Return to program execution

4
External Interrupt Exception Prologue

• STEP 1 SAVE "MACHINE CONTEXT"
• stwu sp, -40 (sp)
• stw r3, 24 (sp)
• mfsrr0 r3
• stw r3, 12 (sp)
• mfsrr1 r3
• stw r3, 16 (sp)
• STEP 2 make execution recoverable and enable
• external interrupt
• mtspr EIE, r3

• Create stack frame, saving r3, SRR0, SRR1
• Must use r3 or some other GPR because SRR01
  cannot be saved directly
• MSREE and MSRRI are cleared, i.e., Interrupt
  disabled and execution notrecoverable

• Set MSREE and MSRRI bits others
• EIE set MSREE and MSRRI
• EID set MSRRI only

5
External Interrupt Exception Prologue (Continue)

• STEP 3 SAVE OTHER APPROPRIATE CONTEXT
• mflr r3
• stw r3, 8 (sp)
• mfcr r3
• stw r3, 20 (sp)
• stw r4, 28 (sp)
• stw r5, 32 (sp)
• stw r6, 36 (sp)

• Save LR and CR
• LR will be changed when calling ISR
• ISR will have branches that change CR
• r3 is used because CR and LR cannot be saved
  into memory directly

• Save other registers
• assume that any ISR uses only r3-r6
• must save more if ISR is written in C

6
MPC555 Interrupt Controller

• Features
• Support sixteen priority levels
• Interrupt masking To help enable and disable
  interrupts selectively
• Interrupt vector code To help generate ISR
  address
• Interrupt prioritization To help select the
  interrupt with the highest priority

7
MPC555 Interrupt Controller
U-BUS
2
IRQ07
8
external
8
3
1
USIU
4
IRQ
1
Reset
1
Timer

• Eight interrupt levels assigned to internal
  devices
• Eight IRQ pins reserved for extern devices
• Hard drive, video card,
• IRQ0 connect to reset

8
MPC555 Interrupt Controller

• Programming interface
• SIPEND Interrupt pending register, recording all
  pending interrupt signals
• SIMASK Interrupt mask register, storing the mask
  bits
• SIVEC Interrupt vector code, storing the vector
  code for the interrupt of the highest priority

9
MPC555 Interrupt Controller

• SIPEND Eight internal interrupt sources, eight
  external interrupt sources interleaved together
• UIPEND is located at UIMB

From IMB3 peripherals
L7 for 7-31
L0
L1
L2
L3
L4
L5
L6
UIPEND
External IRQ07
I1
I2
I3
I4
I5
I6
I7
I0
10
MPC555 Interrupt Controller

• SIMASK 16 effective bits, one for each interrupt
  source

Masked Interrupt Signals 0-15
11
MPC555 Interrupt Controller

• SIVEC Vector code for the most urgent interrupt

Masked Interrupt Signals 0-15
Priority Arbiter Hardware
0
0
X
X
X
X
0
0
SIVEC
Priority 0 Highest
12
MPC555 Exceptions and Interrupts
device 1
device 2
device n

External Interrupts
SIVEC SIMASK SIPEND
Interrupt controller
External interrupt exception
CPU
External Interrupt ESR
Other ESR
Other ESR
ISR 1
ISR 2
ISR n

13
External Interrupt Exception Prologue (Continue)

• STEP 4 DETERMINE INTERRUPT SOURCE
• lis r3, SIVEC_at_ha
• lbz r3, SIVEC_at_l (r3)
• lis r4, IRQ_table_at_h
• ori r4, r4, IRQ_table_at_l
• add r4, r3, r4
• mtlr r4
• STEP 5 BRANCH TO INTERRUPT HANDLER
• blrl

• Load 8-bit SIVEC into r3
• SIVEC here is a 32-bit constant 0x2FC01C

• Set up jump inst address in a jump table
• use lis and ori to load IRQ table base
• add offset to get the ISR address
• move jump inst address to LR

• blrl branch to address in LR and save PC4 in LR
• basically this is a function call using function
  pointer
• at target address b kth_isr_addr

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Set Up ISR Addresses

• Use Jump table
• IRQ_jump_table
• b irq0_handler interrupt pin 0
• b level0_handler interrupt level 0
• b irq1_handler interrupt pin 1
• b level1_handler interrupt level
• b irq7_handler interrupt pin 7
• b level7_handler interrupt level 7
• irq0_hanlder IRQ0 ISR put here

15
Set Up ISR Addresses

• Use address table
• InterruptTable
• .long irq0_handler interrupt pin 0
• .long level0_handler interrupt level 0
• .long irq1_handler interrupt pin 1
• .long level1_handler interrupt level 1
• .long irq7_handler interrupt pin 7
• .long level7_handler interrupt level 7
• irq0_hanlder IRQ0 ISR put here

16
External Interrupt Exception Epilogue

• STEP 6 RESTORE CONTEXT
• lwz r4, 28 (sp)
• lwz r5, 32 (sp)
• lwz r6, 36 (sp)
• lwz r3, 8 (sp)
• mtcrf 0xff, r3
• lwz r3, 20 (sp)
• mtlr r3

Restore r4, r5, r6, which were savedin prologue

• Restore CR and LR
• again use r3 as a bridge
• CR and LR (and any other SPR) cannot be loaded
  directly with data from memory

17
External Interrupt Exception Epilogue (Continue)

• STEP 6 RESTORE CONTEXT
• mtspr NRI, r3
• lwz r3, 12 (sp)
• mtsrr0 r3
• lwz r3, 16 (sp)
• mtsrr1 r3
• lwz r3, 24 (sp)
• addi sp, sp, 40
• STEP 7 RETURN TO PROGRAM
• rfi End of Interrupt

• Clear MSRRI and MSREE
• cannot be interrupted from now on
• NRI SPR for fast clearing MSREE and MSRRI

• Restore SRR0, SRR1 and r3
• again use r3 as a bridge in restoring SRR0 and
  SRR1
• r3 is the first to be saved and the last one to
  be restored

• rfi (return from interrupt)
• restores MSR bits saved in SRR1
• restores next-PC saved in SRR0

18
External Interrupt ESR

• General Setup
• Set up SIMASK
• Set up ISR table
• Set up device interrupt level

19
MPC555 On-Chip I/O
1
2
3
4
5
20
MPC555 On-Chip I/O
TPU3
TPU3
MIOS1
QADC64
QADC64
TouCAN
TouCAN
QSMCM
1
IMB3 Bus

• TPU3 Time Processor Units, 3rd version
  versatile functions, e.g. counting pulses
• MIOS1 Modular I/O System
• QADC64 Queued Analog-to-digital converter
• TouCAN Control Area Network, two-wire, up to
  1Mbps and 40m e.g. network inside vehicle
• QSMCM Queued Serial Multi-channel Module
• IMB3 bus Inter-Module Bus

21
UIMB U-bus to IMB Interface
IMB3 Bus
32
2
addr/data
UIPEND
UMCRIRQUX
8
U-Bus
Other bus
Interruptcontroller

• UIMB U-bus to IMB interface
• UIPEND Interrupt pending reg.
• U-bus Unified bus, connecting multiple internal
  buses
• UMCRIRQUX Enable level 7-31

22
UIMB U-bus to IMB Interface

• The interface converts 32 interrupt levels on
  IMB3 Bus to 8 interrupt levels on U-Bus
• Level 0-6 to U-Bus level 0-6
• Level 7-31 to U-Bus level 7
• Interrupt handler reads full UIPEND through
  memory-mapped I/O

23
Unified System Interface Unit

• The USIU controls system start-up, system
  initialization and operation, system protection,
  and the external system bus.
• MPC555 USIU functions
• System configuration and protection
• Interrupt controller
• System reset monitoring and generation
• Clock synthesizer
• Power management
• External bus interface (EBI) control
• Memory controller
• Debug support

Internal I/O
Processor Core
USIU
24
Unified System Interface Unit
Internal I/Othrough U-bus
External IRQ
USIU
4
Timebase
SIPEND
Clock
SIMASK
PIT
SIVEC
PLL
IREQ
SW watchdog
NMI control
reset
Decr timer
Decrementer
Note External IRQ is controlled by SIEL
triggered by falling edge or low level
25
USIU Internal Interrupt Sources

• MPC 555 has a crystal of 4MHz or 20MHz
• Time base timer interrupt based on the clock
  cannot be reset
• Real-time clock timer interrupt based on
  real-time clock (like a watch) cannot be reset
• PIT Periodic interrupt timer goes off every n
  cycles
• PLL change of lock Phase lock loop, used to
  provide higher clock frequency generate
  interrupt in abnormal situation, e.g. lost the
  lock of the clock
• Software watch dog Used to monitor help avoid
  software deadlock
• Decrementer Another timer interrupt, but is
  processed by a special handler (less overhead)

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Connecting To PowerPC Core
5
Finally!
MSREE
IREQ
Vector table
inst addrto mem
1
n0x100

n0x500
NMI
2
n0x900
Decrementer
3
SRR1
SRR0
inst
Inst buffer

• Three interrupt lines to processor core IREQ,
  NMI, and Decrementer
• MSREE Enable external interrupt
• IREQ External interrupt
• NMI Non-maskable interrupt (e.g. reset button is
  pushed)
• Decrementer fast timer interrupt
• Other processor components not shown

27
Connecting To PowerPC Core

• Refers to three handlers for
• Maskable Interrupt
• Non-maskable interrupt
• Decrementer (low-overhead timer)
• When an interrupt happens, hardware
• Waits for current inst to complete
• Saves PC to SRR0
• Saves MSREE to SRR1, Clear MSREE
• Transfer control to n0x100, n0x500, or n0x900,
  respectively
• The rest is left to software handler
• All I/O interrupts share the same interrupt
  handler