Analog%20Front%20End%20(AFE)%20Boards%20Production%20Testing

1
Analog Front End (AFE) BoardsProduction Testing

• John T. Anderson, Fermilab
• March 22, 2001

• Test and Calibration Overview
• Board Testing at DAB3
• Calibration at Lab 3
• Test Hardware
• Test Software
• Current Allocation of Resources

2
Test and Calibration Overview

• Two separate systems for testing and calibration
• Test stands at DAB3 perform production test
• All boards calibrated relative to each other
  against AFE Test Module
• DAB3 tests sufficient to insure board will work
  on platform
• All functions of board are exercised at DAB3
• Subset of boards taken to Lab3 for absolute
  calibration
• Lab3 data correlates performance using AFE Test
  Module to response against actual VLPC signals

3
Board Testing at DAB3

• Five-Step Test Pipeline
• Inspection Rework
• Unpowered tests
• Programming of PLDs and Microcontroller
• Bench tests of individual functions
• Analog functionality and relative calibration
  against AFETM
• Stages 1 2 require minimal equipment
• Stage 3 requires computer and interfaces
• Stages 4 5 require significant hardware
  expertise

4
Calibration at Lab 3

• Lab 3 provides exact model of platform
  connections
• Lab 3 is difficult environment to work in
• Physically cramped
• Lots of electrical noise
• Necessary for some boards, but impractical to run
  all boards through Lab 3
• Since all boards are run through AFETM,
  correlation of some boards Lab3 results to their
  AFETM results provides relative calibration of
  all boards.
• Estimate that 10 to 15 of all boards should go
  through Lab 3 calibration

5
Test Hardware

• Stage 1 none required
• Stage 2 DVMs only
• Stage 3 PC with Lattice and Microchip software
  interfaces
• Stage 4 PC with Excel/VBA code, Bit 3, VME
  crate, 1553 interface, SASEQ module, Vicor power
  supplies, Rack Monitor, AFE backplane
• two of these test stands have already been built
  and are in use
• Stage 5 Same as Stage 4 plus LVDS test setup and
  AFETM mounted in relay rack
• one of these built but LVDS test setup still not
  codified

6
Test Software

• Software is largest work remaining
• Extant Stage 4 software OK for highly trained
  engineers but not usable for efficient production
  testing
• New software design not required, need work on
  user interface and data logging. Needs to be
  much more automatic than it is now.
• Subroutines and pieces from which Stage 5
  software could be written exist, and structure
  defined, but not yet coded.
• If more hands are to be added, this is the place
  to do it.

7
Allocation of Resources

• Current resource allocation
• Anderson AFETM, 12-MCM (mother daughter)
  redesign, Sanmina, assist with prototype testing
• Matulik prototype testing, test procedure
  documentation
• Zverev prototype testing
• Rubinov Lab 3
• Pei/Moua rework/inspection of remaining
  prototypes
• Sheahan 12-MCM motherboard schematic entry
• Kubik 12-MCM daughterboard schematic entry