1Stanford University

1
10 Tb/s CMOS Switch Fabric Chip

• Patrick Chiang, Ron Ho, Hae-Chang Lee, Brian
  Towles, Vladimir Stojanovic, Mark Horowitz

2
What is possible? (conservative)

• Assumptions 2008 0.1um CMOS Technology
• F04 Delay 50ps
• Minimum Wiring Pitch/signal 0.8um/wire(16l)
• Package 6000 BGA pins
• 2000 power/gnd pins
• 4000 I/O pins gt 2000 differential I/O pins
• First Cut NxN Single Chip Crossbar

3
Single Chip NxN Crossbar
N Outputs
N Inputs
4
NxN Crossbar (revised)

• I/O layout across the chip

5
Interconnect Buffering

• Add buffers,latches for interconnect

6
Background Numbers

• 8mm x 8mm crossbar
• Total capacitance switching/clock cycle
• M1, M2 capacitance 0.3ff/um
• Total wiring capacitance 2.4pF/wire
• 0.6pF buffer capacitance
• 2.4pF 0.6pF 3pF/capacitance per on-chip
  signal
• 0.1um CMOS
• F04 50ps (slow), 35ps (nominal)
• Vdd 1V, f 2Gb/s
• Power
• CVswing2f
• I/O (Ed Lees thesis -- 0.25um CMOS)
• I/O speed 2 F04
• I/O area 500u x 500u
• I/O power 250mW

7
Preliminary Numbers

• Assume 8mm x 8mm crossbar area

8
I/O Bandwidth/Area

• Package 6000 BGA pins(optimistically)
• 2000 power/gnd pins
• 4000 I/O pins gt 2000 differential I/O pins
• ? 1000 x 1000 Crossbar
• Assume in 0.1um, 10Gb/s per I/O (2 F04)
• I/O Bandwidth 10Tb/s
• I/O Area 200um x 200um / signal
• 10009e-4 cm2 0.45cm2
• Total Area 0.64cm2 0.45 cm2 10.3mm x
  10.3mm

9
Total Power

• Wiring Power CV2f 120W
• I/O Power 150mW/link1000 links 150W

• Total Power 120W 200W 270W

• Optical I/O Power and Area???

10
Conclusion

• Possible to achieve 10 Tb/s on single CMOS chip
• Limiting factor is I/O bandwidth, area, power
• How does optics play into this?