The Computer System

1
The Computer System

• Computer components
• CPU Central Processing Unit
• System BUS
• Memory
• Input / Output
• Computer function
• The FETCH-DECODE-EXECUTE cycle
• Interrupts and I/O function

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Computer components

• Von Neumman Architecture
• Data instructions stored in a single read-write
  memory
• The contents of this memory are addressable by
  location (no distinction between Data
  Instructions)
• Execution occurs in a sequential fashion

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von Neumann / Turing

• Stored Program concept
• Main memory storing programs and data
• ALU operating on binary data
• Control unit interpreting instructions from
  memory and executing
• Input and output equipment operated by control
  unit
• Princeton Institute for Advanced Studies
• IAS
• Completed 1952

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IAS - details

• 1000 x 40 bit words
• Binary number
• 2 x 20 bit instructions
• Set of registers (storage in CPU)
• Memory Buffer Register
• Memory Address Register
• Instruction Register
• Instruction Buffer Register
• Program Counter
• Accumulator
• Multiplier Quotient

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Computer components Top level view
System BUS
CPU
I/O module
Memory
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The control unit rôle

• Each instruction has a unique code
• Ex 001 ADD x
• 010 MOVE x, y
• 100 NOT
• The code is recognized and the control signals
  are activated
• We have a computer ?

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Execution

• CPU (microprocessor) and Memory
• Data transfer CPU ? Memory
• CPU and I/O modules
• Data transfer CPU ? I/O modules
• Data processing
• Arithmetical and Logical operations on data
• Control
• Program control flow (ex jump)
• A combination of all above

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Computer function

• Basic Instruction cycle FETCH-DECODE-EXECUTE

Fetch Cycle
FETCH next instruction
DECODE EXECUTE instruction
Decode Execute cycle
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The FETCH-DECODE-EXECUTE detailed

• Instruction fetch
• Instruction (Memory) ? IR Instruction Register
• Program Counter PC ? PC1 (or other)
• Instruction operation decoding
• (OPCODE interpretation)
• Data (operand) localization (calculation), if any
• Data (operand) fetch, from memory or I/O
• Data operation - execute the operation
• Operand store
• GOTO Instruction fetch

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A memory location What? A Word (ex 16 bits)

• Instruction format
• OPCODE - 4 bits
• 24 16 different OPCODES

• Data (integer) format
• Signed integers from (215-1) -32767
• to 215-1 32767

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A memory location How many?

• Addresses coded with 12 bits (in the example)
• Total address space 212 4096 (4Kb)
  memory locations

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Memento (1)

• Binary representation

0 1 0 0 1 0 1 0
1 byte 8 bits 1 Kilo byte 1024 bytes

• Possible interpretation

0 1 0 0 1 0 1 0
Value (contents) Position
7 6 5 4 3 2 1 0
Decimal equivalent of the binary value
0x271x260x250x241x230x221x210x20 74
(decimal)

• Total number of different codes in field of 8
  bits
• 28256 (Why?)

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Memento (2)

• The maximum unsigned integer to be binary coded
  on n-places 2n-1
• Binary to Hexadecimal representation

0 1 0 0 1 0 1 0 0 0 1 0 1 1 1 0 binary
4 A 2 D hexadecimal
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Example of program execution (definition)

• Systems word 16 bits
• Instruction format
• OPCODE on 4 bits
• operand address 12 bits
• Data format signed integer 16 bits
• Addressable memory (12 bits) 4K of words
• CPU Registers
• PC Program Counter Instruction address
• IR Instruction Register Instruction being
  executed
• AC Accumulator Temporary storage register
• Instruction OPCODES
• 0001 Load AC from Memory
• 0010 Store AC to Memory
• 0101 Add to AC from Memory

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Example of program execution
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Instruction cycle state diagram
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Interrupts

• Mechanism by which other modules (I/O, Memory)
  may interrupt the normal processing of the
  processor
• Terminology
• Interrupt request
• Interrupt acknowledge
• Interrupt handler (service) routine

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Instruction cycle with Interrupts
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Interrupts

• Classes of interrupts
• PROGRAM (ex overflow, division by zero)
• TIMER (ex multitasking)
• I/O (ex normal communication signals, or error)
• Hardware failure (ex memory read failure)

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Program flow without / with interrupts
21
Transfer of control via Interrupts
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Interruption cycle Interruption processing

• Attached to the instruction cycle
• mP checks if any interrupts have occurred
• Interruption are signaled by interrupt signal
• IF no interruption THEN fetch next instruction
• ELSE
• Suspends execution of the current program
• Saves the context (next instruction address (PC)
  any other relevant data)
• PC ? address of the interrupt handler routine
• Interrupt handler program execution
• Taking back the context and continue

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Multiple Interrupts

• Disable interrupts
• Processor will ignore further interrupts whilst
  processing one interrupt
• Interrupts remain pending and are checked after
  first interrupt has been processed
• Interrupts handled in sequence as they occur
• Define priorities
• Low priority interrupts can be interrupted by
  higher priority interrupts
• When higher priority interrupt has been
  processed, processor returns to previous
  interrupt

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Multiple Interrupts - Sequential
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Multiple Interrupts Nested
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Time Sequence of Multiple Interrupts