GCT algorithms in TDR design

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GCT algorithms in TDR design

• Greg Heath, University of Bristol

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Overview of algorithms

• Algorithm stages in jet and energy sum logic
• Processing flows from left to right

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Implementation status

• Sort algorithm fully tested
• Jet finder and missing Et studied in simulation
• Available for recycling if needed
• Electron sort
• Missing Et

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Overview of algorithms (ii)

• Similar view of the new system

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(old) Jet finder algorithm

• Implement full sliding 3?3 window
• One FPGA (central ? region) looks at a (f,?)
  strip 2?14 cells
• 4?16 energies input
• Data copying
• 143 of aggregate input data copied between FPGAs
• One third transmitted over backplane links
• Design and implementation by Rob Frazier and Dave
  Newbold

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Sort algorithm

• Several VHDL sort algorithms in CMS!
• GCT version designed to minimise logic usage for
  low-latency 72?12?4 tree
• Initially in an ASIC (U. Schäfer)
• Implemented and tested by Jim Brooke in 2001-02
• Flexible, cascadable n?4 Sort

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Energy sums and Etmiss

• Work out Etv(Ex²Ey²)
• Together with corresponding angle
• Uses Virtex-II fast multiply blocks
• Designed and implemented by G. Heath
• Now implementing in CMSSW emulator

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