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Algorithmic State Machines Sorting Example

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Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design ... Rj. Legend: position of memory. indexed by i. position of memory. indexed by j ... – PowerPoint PPT presentation

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Title: Algorithmic State Machines Sorting Example


1
Algorithmic State MachinesSorting Example
ECE 545 Lecture 8
2
Sources Required Reading
  • Stephen Brown and Zvonko Vranesic,Fundamentals
    of Digital Logic with VHDL Design
  • Chapter 8.10
  • Algorithmic State Machine (ASM) Charts
  • Chapter 10.2.6
  • Sort Operation
  • (handouts distributed in class)

3
Algorithmic State Machine (ASM) Charts
4
Algorithmic State Machine
  • Algorithmic State Machine
  • representation of a Finite State Machine
  • suitable for FSMs with a larger number of
    inputs and outputs compared to FSMs expressed
    using state diagrams and state tables.

5
Elements used in ASM charts (1)
State name
Output signals
0 (False)
1 (True)
Condition
or actions
expression
(Moore type)
(a) State box
(b) Decision box
Conditional outputs
or actions (Mealy type)
(c) Conditional output box
6
Elements used in ASM charts (2)
  • State box represents a state.
  • Equivalent to a node in a state diagram or a row
    in a state table.
  • Moore type outputs are listed inside of the box.
    It is customary to write only the name of the
    signal that has to be asserted in the given
    state, e.g., z instead of z1. Also, it might be
    useful to write an action to be taken, e.g.,
    Count Count 1, and only later translate it to
    asserting a control signal that causes a given
    action to take place.

7
Elements used in ASM charts (3)
  • Decision box indicates that a given condition
    is to be tested and the exit path is to be chosen
    accordingly
  • The condition expression consists of one or more
    inputs to the FSM.
  • Conditional output box denotes output signals
    that are of the Mealy type. The condition that
    determines whether such outputs are generated is
    specified in the decision box.

8
Moore FSM Example 1 State diagram
Reset
w
1



B
z
0

A
z
0

w
0

w
0

w
0

w
1

C
z
1


w
1

9
ASM Chart for Moore FSM Example 1
10
Mealy FSM Example 2 State diagram
11
ASM Chart for Mealy FSM Example 2
12
Control Unit Example Arbiter (1)
reset
r1
g1
Arbiter
g2
r2
g3
r3
clock
13
Control Unit Example Arbiter (2)
14
Control Unit Example Arbiter (3)
15
ASM Chart for Control Unit - Example 3
16
Digital System Design with VHDL
17
Structure of a Typical Digital System
Data Inputs
Control Inputs
Control Signals
Execution Unit (Datapath)
Control Unit (Control)
Data Outputs
Control Outputs
18
Hardware Design with RTL VHDL
Interface
Pseudocode
Control Unit
Execution Unit
Block diagram
Block diagram
ASM
VHDL code
VHDL code
VHDL code
19
Sorting
20
Sorting - Required Interface
Sort
Clock
Resetn
N
N
DataIn
DataOut
L
RAdd
Done
WrInit
S (0initialization 1computations)
Rd
21
Simulation results for the sort operation
(1)Loading the registers and starting sorting
22
Simulation results for the sort operation
(2)Completing sorting and reading out registers
23
Sorting - Example
During Sorting
After sorting
Before sorting
i0 i0 i0 i1 i1 i2 j1 j2 j3 j2 j3 j3
address
0 1 2 3
3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2 4 4 4 4 4 4 4 3
1 1 1 1 2 2 3 4
Legend
position of memory indexed by i
position of memory indexed by j
Rj
Ri
24
Pseudocode for the sort operation
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