Switch Interface

1
Switch Interface
16x16 Switch
16 lvds pairs
16 lvds pairs
Lvds clock
Lvds clock
Start
Valid data
Reset
Pll locked
Config modes 1. Test mode (11) 2. Encrypt
mode 3. Decrypt mode
Config mode
Load seed
Seed input (serial)
2
I/O Specifications
3
Block Diagram
Pll locked
LVDS input
PLL
LVDS Output
System clock
Lvds clock
Lvds clock
Switching Matrix
16 lvds data pairs
16 lvds data pairs
Start
Valid data
Delay Module
Config mode
LFSR
Seed input (serial)
Load seed
Reset
4
Seed loading in LFSR
Load seed
seed
1 0
1 0

• Load_seed control signal must be kept high for 56
  clock cycles

5
Configuration Mode
test
Delay Module
Encrypt/ decrypt
1 0
1 0
1 0
1 0
1 0
1 0
Each line corresponds to 8 consecutive signals
from adjacent LFSR registers
LFSR (56 bits)