Advanced Dynamic Logic Styles

1
Advanced Dynamic Logic Styles

• Aiyappan Natarajan
• ECE 697V Paper Presentation

2
Outline

• Conventional Dynamic Logic Styles
• Clock-delayed Domino Logic
• Parallel Dynamic Logic Style
• Locally Clocked Dynamic Logic Style
• Conclusion and future work

3
Conventional Dynamic Logic Styles

• Pull up or pull down only structures
• Dynamic node precharged/predischarged
• Faster than conventional static CMOS
• Wide NOR implementation
• High performance circuits
• Cascading
• Charge Sharing

4
Conventional Domino Logic Style

• Solution to Cascading
• Used in high speed chips such as Alpha 21164
  Microprocessor
• Possible elimination of footer transistor
• Monotonic
• Charge Sharing

5
Clocked-delayed Domino Logic Style

• Removes monotonicity
• Delay the precharge clock using clock-delay logic
  device (CDLD) when necessary
• Provides inverting and non-inverting logic
• Supports Wide NOR/OR gates

G.Yee and C.Sechen,"Clock Delayed domino logic
style",IEEE ICCD'96
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CD Domino Logic Style (Contd.)

• Delay equals worst case pull-down delay
• CDLD not needed if output is not slowest input to
  any gate
• Delay depends on
• Process variations
• Routing
• Coupling parasitics

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Simple Clocking Scheme for CD Domino
dynamic gate
dynamic gate
dynamic gate
primary inputs
dynamic gate
dynamic gate
dynamic gate
fixed delay 1
fixed delay 2
fixed delay 3
clk1
clk2
clk3
clk4
gate level 1
gate level 3
gate level 2
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Merits of CD Domino

• Provides both inverting and non-inverting logic
  gates
• Provides high fan-in NOR and OR gates
• Linear dependence of delay with fan-in
• Improved power dissipation reduction in peak
  power dissipation

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Comparison Results
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Problems With CD Domino Logic Style

• Difficult to design clock-delay
• Delay is sensitive to process variation, routing
  and coupling parasitics
• Additional circuits needed

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Parallel Dynamic Logic (PDL)

• Similar to np-CMOS
• Two clock signals with 180 phase diff.
• Parallel topology
• No charge sharing problems
• Cascading problem

C.Kim,S.Jung,K.Baek, and S.Kang, Parallel
dynamic logic with speed-enhanced skewed static
logic,IEEE symposium on Circuits and system 2000
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PDL With Speed-enhanced Skewed Static (SSS) Logic

• Similar to skewed static logic
• Logic function
• Positive feedback
• Small transistor sizes
• Less input capacitance
• No dynamic floating nodes

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Comparison with CD-Domino

• Energy savings up to 37 compared to
  Clock-delayed domino
• No charge sharing problems
• Suitable for high-speed low voltage digital logic

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Locally Clocked (LC) Dynamic Logic

• Asynchronous dynamic logic pipeline
• Single rail logic
• Similar to True single-phase clock gates
• LC dynamic logic gates
• Dynamic logic portion
• Latching section

G.Hoyer, G.Yee, and C.Sechen, Locally clocked
pipelines and dynamic logic IEEE trans. On VLSI
systems, Feb 2001.
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LC Dynamic Logic (contd.)

• Fully pipelined logic
• One gate level per stage
• Uses Locally clocked pipeline technique
• Delay matching in controller to produce correct
  handshaking signals

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LC Control Technique

• Uses a clock controller (CC) Element
• Better drive and input cap compared to full
  Muller C-element
• Delay bounded
• Delay matching to enforce timing constraints

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Timing constraints for evaluation phase

• Inputs to stage i must be in their final values
• Successor stage must have consumed previous data
  token
• All gates in stage i must be fully precharged
• Successor stage i1 must have started evaluating
  the new token before stage i enters precharge

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Multiplier using LC dynamic Logic

• 8x8 multiplier using carry-save architecture
• Wide NORs implemented
• 2 stage for carry and sum logic
• Maximum frequency 715 Mhz
• 3.4 sq. mm of Silicon using 1um process
• 32 less energy and 54 greater frequency than
  delay-insensitive implementation (using full
  muller-C element)

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Conclusions

• CD-domino solves the monotonicity problem in
  domino
• Delay dependent on process variations
• PDL with SSS
• Requires no additional circuits
• Easy to design
• LC Dynamic logic
• Fully pipelined
• Delay-bounded pipelining

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Future Work

• Impact of process variation in delay elements
• Impact of scaling
• Application and Design Issues
• Reliability
• Design and Effort time

21
References

• G. Yee and C.Sechen, Clock-Delayed Domino for
  Adder and Combinational Logic design, IEEE ICCD
  1996.
• C. Kim, S.Jung,K. Baek and S.Kang, Parallel
  Dynamic Logic with Speed-Enhanced Skewed Static
  Logic,IEEE International Symposium on Circuits
  and Systems pp 756-759 , 2000.
• G. Hoyer, G. Yee and C. Sechen, Locally Clocked
  Pipelines and Dynamic Logic, IEEE Trans. On VLSI
  Systems, Vol.10, No.1 Feb. 2001.