A HighSpeed Wide Tuning Range 2'8GHz 10'3GHz Digitally Controlled Oscillator in 90nm CMOS

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A High-Speed Wide Tuning Range (2.8GHz - 10.3GHz)
Digitally Controlled Oscillator in 90nm CMOS

• By Sabrina Liao
• Summer 2007
• Supervisor Professor A. Chan Carusone

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Presentation Outline

• Motivations
• Circuit Design
• Results and Comparison
• Future Work and Conclusion

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Motivations

• Some background on wireless communication devices

Frequency Allocation
Phase Locked Loop (PLL) generates clock signals
phase comparator
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Motivation 1

• Desire for increased mobility

Smaller chips
Smaller feature size
Lower supply voltage
Digital PLL will function
Analog VCO may not function Digital / analog
interface difficult to achieve
Solution Digitally Controlled Oscillator (DCO)
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Motivation 2

• Next generation of wireless systems (4G) will
  likely combine all of the following access
  technologies into one network (2.4GHz 10.6GHz)

Frequency Allocation
Logical Solution wide tuning range DCO that
saves space as well as power
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Presentation Outline

• Motivations
• Circuit Design
• Results and Comparison
• Conclusion

• Digital control
• Wide tuning range

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Background on Oscillator Design
1
0
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Proposed DCO Topology
input
input
Input Conversion Block
input
5-bit Input
Control Blocks
Ring Oscillator
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Result Multiple Tuning Curves
3 possible oscillator configurations and their
frequency tuning curves
All stages activated
6 stages activated
4 stages activated
3-bit input to Control Blocks
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Presentation Outline

• Motivations
• Circuit Design
• Results and Comparison
• Conclusion

• Digital control
• Wide tuning range

• 5 papers published in 2006 and 2007
• 3 touchstones power consumption, phase noise,
  tuning range

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Comparison with State of the Art
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Comparison with State of the Art
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Comparison with State of the Art
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Future Work

• Layout the design in 90nm
• Estimated area 300um x 300um
• Total transistor count 175
• Submit design in October
• Testing in March next year

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Conclusion

• Digitally controlled oscillators with a wide
  tuning range is necessary for the next generation
  of wireless systems.
• The proposed DCO uses a novel architecture which
  can be programmed to output three different
  frequency curves.
• Performance of the proposed DCO
• Power consumption 2.8mW _at_ 6.5GHz
• Phase noise -108dBc/Hz _at_ 6.5GHz, 10MHz offset
• Tuning Range 2.8GHz 10.3GHz

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Acknowledgement

• Supervisor Professor A. Chan Carusone
• Ph.D. Candidate Mike Bichan

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References

• Rezayee, A. Martin, K., A coupled two-stage
  ring oscillator, Circuits and Systems, 2001.
  MWSCAS 2001. Proceedings of the 44th IEEE 2001
  Midwest Symposium onVolume 2,  14-17 Aug. 2001.
• Rylyakov, A.V. Tierno, J.A. English, G.J.
  Friedman, D. Megheli, M., A Wide Power-Supply
  Range (0.5V-to-1.3V) Wide Tuning Range (500
  MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm
  SOI, Solid-State Circuits Conference, 2007.
  ISSCC 2007. Digest of Technical Papers. IEEE
  International, 11-15 Feb. 2007.
• Oh, Do-Hwan Kim, Deok-Soo Kim, Suhwan Jeong,
  Deog-Kyoon Kim, W., A 2.8Gb/s All-Digital CDR
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  Varactor Pairs, Circuits and Systems, 2007.
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