Sistemi Elettronici - PowerPoint PPT Presentation

1 / 73
About This Presentation
Title:

Sistemi Elettronici

Description:

L1 - MZ. Static CMOS Circuit. At every point in time (except during the switching ... circuit class, which. relies on temporary storage of signal values on the ... – PowerPoint PPT presentation

Number of Views:48
Avg rating:3.0/5.0
Slides: 74
Provided by: maurizio4
Category:

less

Transcript and Presenter's Notes

Title: Sistemi Elettronici


1

2
COMBINATIONAL LOGIC
3
Overview
4
Combinational vs. Sequential Logic
5
Static CMOS Circuit
6
Static CMOS
7
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
8
PMOS Transistors in Series/Parallel Connection
9
Complementary CMOS Logic Style Construction
(cont.)
10
Example Gate NAND
11
Example Gate NOR
12
Example Gate COMPLEX CMOS GATE
13
4-input NAND Gate
Vdd
Out
GND
In1
In2
In3
In4
14
Standard Cell Layout Methodology
15
Two Versions of (ab).c
16
Logic Graph
17
Consistent Euler Path
18
Example x abcd
19
Properties of Complementary CMOS Gates
20
Transistor Sizing
21
Propagation Delay Analysis - The Switch Model
22
What is the Value of Ron?
23
Numerical Examples of Resistances for 1.2mm CMOS
24
Analysis of Propagation Delay
25
Design for Worst Case
26
Influence of Fan-In and Fan-Out on Delay
27
tp as a function of Fan-In
28
Fast Complex Gate - Design Techniques
29
Fast Complex Gate - Design Techniques (2)
30
Fast Complex Gate - Design Techniques (3)
31
Fast Complex Gate - Design Techniques (4)
32
Example Full Adder
33
A Revised Adder Circuit
34
Ratioed Logic
35
Ratioed Logic
36
Active Loads
37
Load Lines of Ratioed Gates
38
Pseudo-NMOS
39
Pseudo-NMOS NAND Gate
VDD
GND
40
Improved Loads
41
Improved Loads (2)
42
Example
43
Pass-Transistor Logic
44
NMOS-only switch
45
Solution 1 Transmission Gate
46
Resistance of Transmission Gate
47
Pass-Transistor Based Multiplexer
S
VDD
GND
In1
In2
S
48
Transmission Gate XOR
49
Delay in Transmission Gate Networks
50
Elmore Delay (Chapter 8)
51
Delay Optimization
52
Transmission Gate Full Adder
53
(2) NMOS Only Logic Level Restoring Transistor
54
Level Restoring Transistor
55
Solution 3 Single Transistor Pass Gate with VT0
56
Complimentary Pass Transistor Logic
57
4 Input NAND in CPL
58
Dynamic Logic
59
Example
60
Transient Response
61
Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
f
GND
62
Reliability Problems Charge Leakage
63
Charge Sharing (redistribution)
64
Charge Redistribution - Solutions
65
Clock Feedthrough
66
Clock Feedthrough and Charge Sharing
67
Cascading Dynamic Gates
68
Domino Logic
69
Domino Logic - Characteristics
70
np-CMOS
71
np CMOS Adder
72
Manchester Carry Chain Adder
73
CMOS Circuit Styles - Summary
Write a Comment
User Comments (0)
About PowerShow.com