The BTeV Vertex Trigger

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The BTeV Vertex Trigger

• Beauty 2002, June 17-21
• Charles Newsom, The University of Iowa
• for
• The BTeV Collaboration

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BTeV detector
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Simulated B Bbar event-including neutrals
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Silicon pixel detector
14,080 pixels (128 rows x 110 cols)
total of 23Million pixels in the full pixel
detector
380,160 pixels per half-station
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BTeV trigger block diagram
200 MB/s (4x compression)
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Level 1 vertex trigger architecture
30 station pixel detector
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L1 vertex trigger algorithm
FPGA Segment Finder (Pattern Recognition)

• Find beginning and ending segments of tracks from
  hit clusters in 3 adjacent stations (triplets)
• beginning segments required to originate from
  beam region
• ending segments required to project out of pixel
  detector volume

DSP Tracking and Vertexing

• Match beginning and ending segments found by FPGA
  segment finder to form complete tracks.
• Reconstruct primary interaction vertices using
  complete tracks with pTlt1.2GeV/c.
• Find tracks that are detached from
  reconstructed primaries.

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L1 vertex trigger algorithm
Execute Trigger
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L1 trigger efficiencies
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L1 vertex trigger work-in-progress

• Status of L1 track finding vertexing code
• C version of full tracking vertexing code
  running on a TI C6711 based daughter card on the
  prototype board.
• Goal is to avoid hand optimized assembly for the
  TI DSP in order to simplify code maintenance and
  achieve greater portability.
• Incorporating various optimizations in C use of
  intrinsics, in-line code vs. external function
  calls, single precision arithmetic, etc.
• Current code speed tests are 4x slower than in
  the proposal using todays technology.

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Level 1 Vertex Code Benchmarks
Pentium III
PowerPC G4
BTeV Proposal
TI DSP
Execution speed in units normalized to TI C6711
speed (longer bars are better)
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L1 trigger 4-DSP prototype board
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Level 2 Trigger

• Start with the Level 1 tracks from the
  triggering collision within the crossing.
• Search for pixel hits along these tracks.
• Refit the tracks using a Kalman Filter.
  Resultant momenta are improved to about 5-10.
• Resultant event must satisfy one of the two
  following criteria
• A secondary vertex must be present or
• The collection of tracks must satisfy a minimum
  pT cut.
• The combined L1 and L2 rejection is 1000-1.
• Overall Efficiency is roughly 50 for most B
  decays of interest.

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Fault tolerant trigger DAQ system

• Summary
• The L1/L2 vertex trigger is a major component in
  the larger framework of the Global BTeV trigger
  and DAQ system.
• This larger framework is a massive and complex
  real-time system involving thousands of FPGAs,
  DSPs, and PCs analyzing detector data generated
  at 1.5 Terabytes/s.
• BTeV will benefit from an NSF grant to develop a
  semi-autonomous, self-monitoring, fault-tolerant
  / adaptive system for this purpose.
• Project involves collaboration of computer
  scientists and physicists from Vanderbilt,
  Illinois, Syracuse, Pittsburgh, and Fermilab
  known as the Real Time Embedded Systems (RTES)
  Research Group.
• The BTeV trigger can be built with currently
  existing technology and will only improve as
  computing technology advances.