A2D Receiver System

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A2D Receiver System
ECEN 5007 Mixed-Signal IC Design

• Michael Sheperek
• Sehin Kebede
• Preeti Bhandarkar
• Chetan Shah

December 5, 2002
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System Block Diagram
A2D Receiver System
December 5, 2002
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Functional Block Diagram
A2D Receiver System
December 5, 2002
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Project Overview
A2D Receiver System
December 5, 2002

• Design a high-speed comparator
• Design a PLL for Random NRZ data capable of
  handling strings of ONEs and ZEROs
• Combine the PLL with a double-edge triggered
  D-flip flop to complete the Clock/Data Recovery
  circuit
• Convert the serial stream of data to a byte-wide
  data

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System Schematic
A2D Receiver System
December 5, 2002
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Use of Comparator
A2D Receiver System
December 5, 2002

• The comparator with a post sampler performs
  the task of 1-bit fast ADC,i.e, It samples the
  incoming waveform and outputs a 1-bit digital
  signal.
• The output of the analog front end supply the
  ADC (the Comparator)with a 500mVpp continues
  signal.
• The high-speed comparator compares this input
  with a reference signal and by doing that it
  converts the incoming signal to a rectangular
  pulses.

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Comparator(Initial)
A2D Receiver System
December 5, 2002
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Comparator(Final)
A2D Receiver System
December 5, 2002
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Simulation Result(Gain Phase)
A2D Receiver System
December 5, 2002
Without Buffer
With Buffer
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Simulation Result(Hysteresis)
A2D Receiver System
December 5, 2002
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Simulation Result(Noise Reduction)
A2D Receiver System
December 5, 2002
Without Hysteresis
With Hysteresis
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Simulation Result(Propagation Delay/Slew Rate)
A2D Receiver System
December 5, 2002
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Simulation Result(Comparator Input Output)
A2D Receiver System
December 5, 2002
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The Comparator Design
A2D Receiver System
December 5, 2002
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Theory of PLL
A2D Receiver System
December 5, 2002

?(s)
Vcntrl(s)
H(s)
?
-
Zeros become poles of A(s)
F(s)
Poles become zeros of A(s)
In General A(s) Closed Loop Gain T(s) Loop
Gain H(s) Feed forward TF F(s) Feed back TF
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Theory of PLL
A2D Receiver System
December 5, 2002

?(s)
Vcntrl(s)
Hcp_lp(s)
?
-
Fvco(s)
Where
phase detector and charge pump
Voltage controlled oscillator (model as an
integrator)
K1 FF constant (V/?) K2 FB constant (?/V)
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Theory of PLL
A2D Receiver System
December 5, 2002
Where
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Phase Frequency Detector
A2D Receiver System
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Timing Waveform
A2D Receiver System
December 5, 2002
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False Lock Problem
A2D Receiver System
December 5, 2002
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False Lock-Timing Waveform
A2D Receiver System
December 5, 2002
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Ideal Charge Pump LPF
A2D Receiver System
December 5, 2002
The Charge Pump is used to convert the digital
pulse up/down into a behaved voltage,
proportional to the up/down signals. The Loop
filter is used to control the rate of change of
the output voltage.
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Charge-Pump Low Pass Filter
A2D Receiver System
December 5, 2002
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Voltage-Controlled Oscillator
A2D Receiver System
December 5, 2002
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Delay-Cell
A2D Receiver System
December 5, 2002
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Why this VCO?
A2D Receiver System
December 5, 2002

• Achieves high rejection of supply and substrate
  noise
• Yields 50 duty cycle, an important requirement
  in timing applications
• Capacitive tuning
• Susceptible to noise
• Substantial variation in gain of VCO
• Min value of C exists at all times
• Resistive tuning
• Large, relatively uniform frequency variation
• Additional circuitry for constant gain swing

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Diff-to-Diff
A2D Receiver System
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Simulation Result(VCO)
A2D Receiver System
December 5, 2002
Without Diff-to-Diff
With Diff-to-Diff
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D-Flip Flop
A2D Receiver System
December 5, 2002
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Simulation Result(250MHz Preamble)
A2D Receiver System
December 5, 2002
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Simulation Result(500MHz Preamble)
A2D Receiver System
December 5, 2002
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Simulation Result(Random Data)
A2D Receiver System
December 5, 2002
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Simulation Result(FM Data)
A2D Receiver System
December 5, 2002
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PLLs Simulated Performance
A2D Receiver System
December 5, 2002
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Serial to Parallel
A2D Receiver System
December 5, 2002
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Simulation Result(Parallel Data)
A2D Receiver System
December 5, 2002
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Workaround Strategies
A2D Receiver System
December 5, 2002

• Operate the system in the range such that the
  problem of harmonic and sub-harmonic frequency
  does not arise
• Use a different architecture for PFD
• Use an additional logic at the output of PFD such
  that the system is stable and still able to avoid
  the 1-1 short circuit stage of charge pump

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Conclusion
A2D Receiver System
December 5, 2002

• High-speed Comparator (with hysteresis) was
  designed
• Few issues with propagation delay
• A PLL was designed for the given operating
  frequency range
• Few issues with false lock and stability
• Synthesizable double-edge triggered D-flip flop
  designed
• Serial to parallel conversion block included for
  completeness
• Work around strategies proposed