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Design ITWG Contributions to ITRS

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Five technology areas: design process, system-level design, logical/physical ... MEMS, Chemical Sensors in production on standard CMOS process push out one year ... – PowerPoint PPT presentation

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Title: Design ITWG Contributions to ITRS


1
Design ITWG Contributions to ITRS
  • System Drivers Chapter
  • Defines IC products that drive manufacturing and
    design technologies
  • ORTCs System Drivers framework for technology
    requirements
  • Three System Driver classes
  • MPU
  • SOC (Low-Power, High-Performance,
    Mixed-Technology)
  • Mixed-Signal
  • Design Chapter
  • Design cost and productivity models
  • Five technology areas design process,
    system-level design, logical/physical/circuit
    design, design verification, design test
  • Cross-cutting challenges productivity, power,
    manufacturing integration, interference,
    error-tolerance
  • ORTC support
  • Frequency, Power, Density models

2
Big Picture
  • Message Cost of Design threatens continuation
    of the semiconductor roadmap
  • Design cost model
  • Challenges are now Crises
  • Strengthen bridge from semiconductors to
    applications, software, architectures
  • Hertz and bits are not the same as efficiency and
    utility
  • System Drivers chapter, with productivity and
    power foci
  • Strengthen bridges among ITRS technologies
  • Shared red bricks can be solved (or,
    worked-around) more cost-effectively
  • Manufacturing Integration cross-cutting
    challenge
  • Living ITRS framework to promote consistency
    validation

3
Design-Manufacturing Integration
  • 2001 ITRS Design Chapter Manufacturing
    Integration one of five Cross-Cutting
    Challenges
  • Goal share red bricks with other ITRS
    technologies
  • Lithography CD variability requirement ? new
    Design techniques that can better handle
    variability
  • Mask data volume requirement ? solved by
    Design-Mfg interfaces and flows that pass
    functional requirements, verification knowledge
    to mask writing and inspection
  • ATE cost and speed red bricks ? solved by DFT,
    BIST/BOST techniques for high-speed I/O, signal
    integrity, analog/MS
  • Does X initiative have as much impact as copper?

4
Living ITRS Framework
  • Living roadmap internally consistent,
    transparent models as basis of ITRS predictions
  • ORTCs Models for layout density, system clock
    speed, total system power in various drivers,
    circuit fabrics
  • Visualization tool (at Sematech website) for
    capture, exploration of ITRS models under
    alternative scenarios

5
Core Messages
  • Design Technology interface from semiconductor
    industry to systems and applications markets
  • Cost of Design is a key threat to semiconductor
    productivity
  • Shared Red Bricks
  • Framework for roadmapping that allows principled
    allocation of RD resources across ITRS
    technologies
  • Role of Design Technology in reducing cost of, or
    enabling workarounds for, near-term red bricks
  • Living ITRS

6
SYSTEM DRIVERS CHAPTER
7
New System Drivers
  • Memory
  • Embedded and Standalone
  • Points of contact
  • Yervant Zorian, U.S.
  • Ichiro Yamamoto, Japan
  • Ralf Brederlow, Europe
  • Target 2003 renewal
  • DSP
  • Addition to MPU (processor) discussion
  • Include discussion of architecture, figures of
    merit
  • Points of contact
  • John Cohn, U.S.
  • Ichiro Yamamoto, Japan
  • Jean-Pierre Schoellkopf, Europe
  • Target 2003 renewal

8
SOC-MT Integration Roadmap
  • System Drivers Figure 10
  • FRAM in production on standard CMOS process
  • Could not find instances of MEMS, Chemical
    Sensors in production on standard CMOS process
    ? push out one year
  • Point of contact
  • Ichiro Yamamoto, Japan
  • Target 2002 update
  • Economic constraints and system-in-package
    integration alternatives
  • Very large set of issues (testability and test
    cost, die cost modeling, performance/cost
    tradeoffs, etc.), possible for 2003 renewal
  • Points of contact
  • Leon Stok, U.S.
  • Ichiro Yamamoto, Japan

9
SOC-LP PDA Model (1)
  • Overall points of contact
  • Kunio Uchiyama, Japan
  • Res Saleh, U.S.
  • System Drivers Table 11 match with Table 36
    (PIDS)
  • Point of contact Andrew Kahng, U.S. Target
    2003
  • LOP/LSTP subthreshold currents (Tables 11, 36)
    too low?
  • Cross-ITWG issue must review with PIDS ITWG
    Target 2003
  • Points of contact
  • John Cohn, David Blaauw, Dennis Sylvester, U.S.
  • Kunio Uchiyama, Japan
  • Table 10 (functional requirements of SOC-LP
    model)
  • Update in 2003
  • Mixed-signal content (e.g., Bluetooth)
  • Affects die area usage, power budget, ATE and
    test strategy, etc.
  • Hard to model (Gary Smith, U.S. will provide
    available data)

10
SOC-LP PDA Model (2)
  • Technology baseline
  • Japan will update from 1999 to 2001 numbers, if
    applicable
  • Performance and Die Size follow historical trends
  • Performance 1000x / 10 years
  • Die size 100mm2 20/4yrs
  • Device and memory composition
  • logic vs. memory, HP vs. LP, SRAM vs. eDRAM
  • Japan PIDS and Design are reviewing (target March
    2003, on agenda for 2002 Tokyo discussion)
  • Dataquest/SI2 study results can be forwarded for
    validation (Gary Smith, U.S.)
  • Battery technology
  • 7-8/year historical improvement will be used in
    Table 12
  • Potential 10x from fuel cells
  • Japan Design is reviewing (target March 2003)

11
Low-Cost, Low-Metal Layer Count Technology
  • Should a separate low-cost, low-metal layer
    technology be roadmapped?
  • Driven by cost, integratability
  • Cf. dynamics of FPGA, microcontroller markets
  • Will wait until question is better defined by
    Europe
  • Target 2003 renewal (if material added into
    roadmap)
  • Points of contact
  • Jean-Pierre Schoellkopf, Ralf Brederlow, Europe

12
Reorganized System Drivers Chapter
  • Change to SOC-centered organization
  • SOC unifying context for various blocks and
    fabrics
  • Processor
  • Memory
  • Mixed-Signal
  • Agreed to at Erlangen meeting
  • Point of contact (mostly editorial function)
  • Andrew Kahng, U.S.
  • Target 2003

13
DESIGN CHAPTER
14
Analog and Circuits Content
  • Feedback from U.S., Europe is that more
    standalone analog, circuits content needed
  • Existing content can be better highlighted by
    chapter reorganization
  • All tables of Difficult Challenges written so
    that issues are specific to a driver class (AMS,
    MPU, SOC)
  • Prototype Table 16 in 2001 ITRS (Design
    Verification)
  • Points of contact
  • Prashant Saxena, John Cohn, U.S.
    (analog/circuits)
  • Ralf Brederlow, Europe (analog/circuits)
  • Andrew Kahng, U.S. (reorganization of material)
  • Target 2003

15
Refinement of Design Cost Metrics
  • Observation predicted memory content of
    constant design cost SOC is higher than industry
    data points
  • Original model was calibrated for high-end
    designs
  • Cost of memory design was assumed to be zero
  • Impacts of current and future design technology
    improvements are difficult to calibrate
  • Better calibration and model refinement in 2003
  • N.B. power models also suggest higher memory
    content than is observed
  • Cost model description needs more clarity
  • Points of contact
  • Gary Smith, Res Saleh, U.S.
  • Ichiro Yamamoto, Japan
  • TBD, Europe
  • Target 2003 renewal

16
Design System Architecture and Flow
  • Motivation super-exponential complexities of
    the design problem require more attention to the
    architecture of future design systems
  • Issues infrastructure, design environment, etc.
  • Design system architecture discussion may be
    added in 2003
  • Related issue flow content in Design Chapter
  • Canonical design flow has been defined by
    STRJ-WG1
  • May be used in 2003
  • Points of contact
  • John Darringer and Don Cottrell, U.S.
  • Ichiro Yamamoto, Japan
  • TBD, Europe

17
SEU (Soft Error)
  • Proposal to increase content on SEU
  • Issues include BIST, BISR, redundancy and other
    forms of error-tolerance
  • Target 2003
  • Points of contact
  • Yervant Zorian, U.S. (working with Victor
    Zhirnov, Sematech SER Working Group)
  • Jean-Pierre Schoellkopf, Europe
  • Don Edenfeld, Test ITWG

18
Cross-ITWG Interactions
  • Interconnect BEOL Architecture Optimization
  • Is low-k (e.g., reduction from 3.0 to 2.8) worth
    it? If we stop at 2.0, will the world end?
  • What is the optimal interconnect stack that
    satisfies via and (damascene copper) metal aspect
    ratio constraints?
  • What is the variability (copper dishing and
    erosion, or poly CD control) that designers can
    tolerate?
  • What ground rules (poly half-pitch, contacted M1
    pitch, ) comprise the tightest limiters on
    layout density?
  • Points of Contact
  • Dennis Sylvester, Andrew Kahng, John Cohn, Kerry
    Bernstein, U.S.
  • Ichiro Yamamoto, Japan
  • Chris Case (Interconnect ITWG) for list of
    constraints from Interconnect (ARs, local metal
    width vs. pitch, via reliability/stacking, )

19
Cross-ITWG Interactions
  • Assembly and Packaging, Factory Integration,
    Test)
  • What are limits on off-chip signaling speed
    imposed by ESD protection?
  • Assembly and Packaging, Environmental Safety and
    Health
  • What are high-performance (MPU) system power
    requirements?
  • resource reduction requirement for
    environmental safety
  • Various First Red limits for 2003 renewal, as
    part of Chip Size Study Group interactions

20
Summary
  • System Drivers Chapter
  • New material
  • Memory
  • DSP
  • Improvements to existing material
  • SOC-MT integration timeline
  • SOC-LP device and system parameters
  • SOC-centric chapter reorganization
  • Design Chapter
  • New material
  • Analog and circuits content
  • Canonical design flow context
  • SEU discussion
  • Improvements to existing material
  • Design cost model refinement
  • Design system architecture
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