UW ASIC Design Team Kickoff

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UW ASIC Design TeamKick-off
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Agenda

• What is an ASIC?
• The levels of an ASIC
• Upcoming projects
• Why join?
• Meeting times and contact info

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What is an ASIC?

• Application-Specific Integrated Circuit
• Customized chip designed for a particular purpose
• System of basic, integrated circuit elements
• Semi-custom ASIC design linking prefabricated
  components with metal layers
• Full-custom ASIC design full control over design
  of mask sets and transistor placement/sizing
• Both analog and digital devices

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Package and Board Level
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Die Level
Phase Locked Loop (PLL)
UltraSPARC
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Design Layout Level
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Upcoming Events

• DAC (47th Design Automation Competition 2010)
• Requires long term commitment
• Design stages include Architecture, RTL
  (Register Transfer Level), Gate Level, Timings,
  and Layout
• Design ideas meeting later this term
• See http//www.dac.com for previous entries

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Current Term

• VHDL Tutorials
• Will be run to get everyone up to a working level
• Starting resources available at
• http//www.ece.uwaterloo.ca/ece223/
• http//www.ece.uwaterloo.ca/ece327/ (Advanced)

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Completed Projects

• 802.11g Transceiver
• Wireless transmitter and receiver
• GZIP
• General purpose decompression
• SRAM
• Static memory storage cell

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Why join the Team?

• Learn skills you normally wouldnt in the
  classroom
• Work on a design from start to finish
• Hardware design experience
• Business/marketing experience
• Potential 4th year design project spin-offs
• OpenRISC 1000 processor
• Design Awards
• Design competitions
• Facilitates Learning
• Lecture series
• ECE 223/222/231/241/327/332/438

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Digital Design

• Learn basics of digital design
• Discover new concepts and see them in action
• DAC design possiblity
• Hardware Ogg Vorbis decoder
• Hardware GZIP decoder

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Analog Design

• Learn basics of semiconductors and analog design
• Discover new concepts and see them in action
• DAC design possibility

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Marketing Team

• Work with the IEEE Student Branch
• Learn business and marketing strategies
• Increase UW ASIC Team visibility on and off
  campus
• Secure sponsors from the industry

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Goals

• Get everyone near the same level of VHDL
• Start the DAC design
• Sign up corporate sponsors
• Long term committed members

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Meetings and Contact Info
DAC Design Meeting, VHDL Tutorials Will contact
by mailing list

• Website www.asic.uwaterloo.ca
• NTP asic.ece.uwaterloo.ca
• Email asicgroup_at_engmail.uwaterloo.ca
• Mailing List

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