Welcome to the ECE 449 Computer Design Lab

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Welcome to the ECE 449Computer Design Lab

• Spring 2005

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ECE 449 Computer Design Lab
Course Coordinator Kris Gaj
Course Instructors, TAs
Monday section Milind M. Parelkar Tuesday
section Milind M. Parelkar Thursday
section Kamal Sayeed
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ECE 449 Computer Design Lab
Change in lab hours
Canceled Section 203 Class time Tuesday,
430-710 PM Created Section 204 Class time
Thursday, 720-1000 PM
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ECE 449 Section Preference Form
First Name Kevin Last Name Smith
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Section Assignment Rules (1)

• Please clearly mark your preferences on
• the distributed form
• Your assignment to a particular lab section will
  be
• determined by Friday, January 28, and sent to
  you
• by e-mail
• You do NOT need to do anything to move to the
  right
• section or move your name from the waiting list
  to the
• registered status
• All assignments are FINAL and cannot be changed
  in
• the middle of the semester

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Section Assignment Rules (2)

• You are welcome to attend any of the
• three office hour sessions
• Please attend the class meetings of the other
  section only
• in case of emergency and give preference in
  access
• to the lab computers to the students attending
• the right section
• All experiment demonstrations and report
  submissions
• need to be done in the presence of your TA, and
  can be
• done exclusively during the class time of your
  section

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ECE 449 Computer Design Lab
Course Instructors, TAs Primary
Responsibilities

• Introductory lectures and hands-on sessions
• Teaching how to use software, hardware and
  testing
• equipment needed for experiments
• - Holding office hours
• Grading student demonstrations and reports

Course Coordinator Primary Responsibilities

• Help in preparation of introductory lectures
• and new experiments
• Coordination of work done by the TAs
• Enforcing consistent policies and grading
  standards
• Mid-semester student satisfaction survey
• Resolving conflicts and providing feedback to TAs

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Lab Access Rules and Behavior Code
Please refer to the FPGA Design Test Lab
website
http//ece.gmu.edu/labs/fpgalab.htm
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Digital Systems Computers
ECE 280
PHYS 261
PHYS 262
? C
or
ECE 331
ECE 332
? C
ECE 445
? C
? C
ECE 442
ECE 449
ECE 447
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Tasks of the course
Advanced course on digital system design with VHDL
Comprehensive introduction to FPGA technology
Testing equipment

• writing VHDL code
• for synthesis
• RTL VHDL
• finite state machines
• test benches

• hardware
• Xilinx FPGAs
• software
• VHDL simulator
• Synthesis tools
• Xilinx ISE

- oscilloscope - logic analyzer
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VHDL for Specification
VHDL for Simulation
VHDL for Synthesis
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Levels of design description
Algorithmic level
Level of description most suitable for synthesis
Register Transfer Level
Logic (gate) level
Circuit (transistor) level
Physical (layout) level
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Register Transfer Logic (RTL) Design Description

Registers
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VHDL Design Styles
VHDL Design Styles
structural
behavioral
Components and interconnects
Concurrent statements
Sequential statements

• Registers
• State machines
• Test benches

Subset most suitable for synthesis
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Testbenches

• Testbench Environment

Stimuli All DUT Inputs
Simulated Outputs
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FPGAs vs. ASICs
FPGAs
ASICs
Off-the-shelf
High performance
Low development costs
Low power
Short time to the market
Low cost (but only in high volumes)
Reconfigurability
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Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be
able to perform an encryption algorithm by
itself, executing 32 rounds..
Specification (Lab Experiments)
VHDL description (Your Source Files)
Library IEEE use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity RC5_core is
port( clock, reset,
encr_decr in std_logic
data_input in std_logic_vector(31 downto 0)
data_output out std_logic_vector(31
downto 0) out_full in
std_logic key_input in
std_logic_vector(31 downto 0)
key_read out std_logic ) end
AES_core
Functional simulation
Synthesis
Post-synthesis simulation
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Design process (2)
Implementation
Timing simulation
Configuration
On chip testing
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Simulation Tools
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Synthesis Tools
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Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is signal
A1STD_LOGIC signal B1STD_LOGIC signal
Y1STD_LOGIC signal MUX_0, MUX_1, MUX_2, MUX_3
STD_LOGIC begin A1ltA when (NEG_A'0')
else not A B1ltB when (NEG_B'0') else not
B YltY1 when (NEG_Y'0') else not
Y1 MUX_0ltA1 and B1 MUX_1ltA1 or
B1 MUX_2ltA1 xor B1 MUX_3ltA1 xnor
B1 with (L1 L0) select Y1ltMUX_0 when
"00", MUX_1 when "01", MUX_2 when
"10", MUX_3 when others end MLU_DATAFLOW
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Implementation

• After synthesis the entire implementation process
  is performed by FPGA vendor tools

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Design Process control from Active-HDL
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XESS Inc. Educational Boards
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FPGA available on the board
Xilinx Spartan 2, XC2S100

• 100,000 equivalent logic
• gates

• 1200 CLB slices

• 10 4-kbit block RAMs

• Up to 200 MHz clock

Block RAMs
Programmable Interconnects
Configurable Logic Block slices (CLB slices)
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Digital system design technologies
ASICs
Microprocessors
FPGAs
Computer Organization
ECE 445 ECE 442 ECE 447
ECE 431
ECE 449
Digital Computer Design Interfacing
Digital Circuit Design
Computer Design Lab
Single Chip Microcomputers
Introduction to VHDL
ECE 545, 645, 681
ECE 545
Microprocessors
ECE 511 ECE 611
Digital Integrated Circuits
Computer Arithmetic
ECE 586 ECE 680
ECE 645
Advanced Microprocessors
VLSI Design Automation
ECE 681
Physical VLSI Design
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STARTING IN SPRING 2006 NEW COURSE
ECE 448, FPGA and ASIC Design with VHDL
Prerequisites ECE 445
Topics covered
VHDL - writing synthesizable RTL level code
in VHDL - writing test benches FPGAs -
architecture of FPGA devices - tools for the
computer-aided design with FPGAs - current
FPGA families future trends
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High-level ASIC Design - standard cell
implementation approach - logic synthesis
tools - differences between FPGA
standard-cell ASIC design flow
Applications Platforms
- basics of computer arithmetic - applications
from communications, coding theory, and
cryptography

• FPGA boards
• microprocessor board FPGA board interfaces
  PCI, PCI-X

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Integration with ECE 449 into one 4 credit hour
course
ECE 449
NEW COURSE, ECE 448
4 credit hours
1 credit hour
VHDL intro FPGA intro ASIC intro more
advanced lectures on applications and platforms
Lab
Lecture
VHDL intro FPGA intro hands-on tools intro
experiment intro lab time
Lab
hands-on tools intro experiment intro lab time
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Why ECE 449 is a challenging course?

• no associated lecture
• need to relearn VHDL
• need to learn tools
• need to perform practical experiments
• time needed to complete experiments
• only one credit hour

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What can not be changed this semester?
Re Organization

• too much work for 1 credit hour

• think positive
• - you pay for one credit hour,
• you are getting three credit hours of
  instruction
• - even if you get a bad grade (gt D)
• it will not ruin your GPA

• your curriculum is a package
• - there are easy courses worth 3 credit hour

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Student self-evaluation Spring 2004
1 better than expected
6 as well as expected
9 worse than expected
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Difficulties Spring 2004

• finding time to do the lab - 6
• too many other classes taken in the
• same semester - 6
• understanding - 4
• getting used to tools - 3
• midterm - 2

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Why is this course worth taking?

• VHDL for synthesis
• one-of-the-most-sought-after skills
• knowledge of state-of-the-art tools used in the
  industry
• knowledge of the modern FPGA technology
• knowledge of state-of-the-art testing equipment
• design portfolio that can be used during job
  interviews
• unique knowledge and practical skills that make
  you
• competitive at the job market