Design Slides for RAD Port to techX http://www.arl.wustl.edu/arl/projects/techX/ppt/RAD_Design_Port_Slides.ppt some slides take from: http://www.arl.wustl.edu/arl/projects/techX/ppt/virtualRouter.ppt

1
Design SlidesforRAD Port to techXhttp//www.ar
l.wustl.edu/arl/projects/techX/ppt/RAD_Design_Port
_Slides.pptsome slides take fromhttp//www.arl.
wustl.edu/arl/projects/techX/ppt/virtualRouter.ppt
John DeHart jdd_at_arl.wustl.edu http//www.arl.wust
l.edu/arl
2
Virtual Networking Basic Concepts
thru channel
substrate link
virtual link
substrate router
virtual router
substrate links may run over Ethernet, IP, MPLS,
. . .
virtual end-system
3
Virtual Router and Substrate

• Virtual routers are constructed from
• Virtual Interfaces (VI) that connect to virtual
  links
• numbered sequentially from 0 for each VR
• have specified bandwidth
• may have internal VLs connecting VRs in same
  substrate router
• Virtual Packet Processors (VPP)
• numbered sequentially from 0
• terminate VIs (one VPP may terminate multiple
  VIs)
• one of several types
• IXP 2850 type (full system of cluster of size 1,
  2, 4, 8 MEs)
• V2Pro P100 (full chip or half chip)
• Virtual Switch (VS)
• has numbered ports that connect to VPPs
• ports have specified bandwidth (input, output may
  differ)
• Control software maps virtual routers onto
  physical resources provided by substrate.

4
Substrate

• Virtual routers are interconnected via Virtual
  Links
• Virtual Links exists within Substrate Links
• Substrate Links are terminated in the Substrate
  of a Substrate Router
• A Substrate Router may contain 0 or more Virtual
  Routers
• A substrate link may contain Virtual Links that
  connect to several different Virtual Routers
• The end of any particular virtual link is
  connected to one and only one Virtual Router

5
Packet Formats

• External packet format (Ethernet)
• Ethernet type field identifies packet as IP
  packet or VNET packet
• VNET packets carry Virtual Link Identifier (VLI)
  and length field
• IP packets treated like VNET packets
• Internal format
• Virtual Router (VR)
• Virtual Destination (VDST)
• format field (3 bits)
• VI, VPP, VPP pair, VPP range
• priority (2 bits)
• destination (2B - VI, VPP, VPP pair, VPP range)
• Physical Destination (PDST)
• Format field (3 bits)
• port, port pair, port range
• priority (2 bits)
• destination (2B - port, port pair, port range)
• Header Error Check (HEC) detects hw faults
• Lookup tables use VRVDST to obtain PDST.

VNET
IP
6
Lookup Tables

• Line card mapping on input.
• for VNET type, map VLI to (VR, VDST, PDST)
• use VR0 to distinguish thru channels
• thru channels are ones ones that do not
  terminate here.
• for IP type, map VLI0 to (VR, VDST, PDST)
• rate limit each outgoing stream as configured
• Line card mapping on output
• map (VR, VDST) to (output interface, Ethernet
  type, VLI)
• rate limit each outgoing stream
• PPC substrate mappings.
• map (VR, VDST) to (local interface, PDST)
• rate limit VI streams from PPs
• Switch elements mapping
• map VR to rate limit for outgoing stream
• per VR queues at each output link
• use PDST for forwarding decisions

7
Control Packets

• We should support a general mechanism for getting
  control information to the VRs.
• Our IPv4 VR will get them as ATM cells embedded
  in packets
• The CCP right now operates on ATM cells so it
  will be easiest to maintain that and have the IN
  module strip the packet away from the embedded
  ATM Cell
• How does the packet get to the VR?
• How does the VR recognize something as control
  vs. data to be routed?
• Proposal
• VI0 Coming in from PPC?

8
Packet Passing Through techX System
VLI
Including Switch Out Port VI VR
Phys Itf, Substrate Link, VLI
Switch
Switch
Switch
9
Packet Passing Through techX System
VR,VI
Switch
Switch
Switch
10
Packet Passing Through techX System
Substrate identifies VR based on
physical Links/signalrs that pkt Came to it on.
Including Switch Out Port VPP VR
VRVPP
Switch
Switch
Switch
11
Packet Passing Through techX System
VR,VPP
Switch
Switch
Switch
12
Packet Passing Through techX System
Including Switch Out Port VI VR
VR,VI
Switch
Switch
Switch
13
Packet Passing Through techX System
VI,VR
Switch
Switch
Switch
14
Packet Passing Through techX System
Switch
Switch
Switch
15
IPv4 Virtual PP

• PP Card Substrate
• Identifies packet as for a VR on this card
• Sends packet to PP/H

VI
Switch
Switch
Switch
16
IPv4 Virtual Packet Processor
SRAM
SRAM
TCAM
QM
RSQ
IN
CRL
from virtual links
OUT
to virtual links
PSM
SDRAM
Plugin Subsystem

• Arriving packets received from multiple virtual
  links.
• Classification Route Lookup (CRL) implements
  route lookup and classification, using VLIIP
  header fields target 20 M lookups/s.
• Packets stored off-chip by PSM, Queue Manager
  (QM) schedules packets for outgoing VLs target
  40 M enqueues/s.
• Resequencer (RSQ) needed for medium, large
  systems.

17
IPv4 Virtual Packet Processor
SRAM
TCAM
SRAM
OUT
IN
CRL
QM
from virtual links
to virtual links
PSM
SDRAM
Plugin Subsystem

• Design Changes in Target System
• Change where plugin subsystem connects
• Have IN store packet payload to PSM/SDRAM
• Have OUT retrieve packet payload from PSM/SDRAM
• No RSQ in this design. It must reside in Switch
  Fabric or at its interface.
• Also need to add CCP in to design

18
IPv4 Virtual Packet Processor
Control Cell Processor (CCP)
SRAM
TCAM
SRAM
OUT
IN
CRL
QM
from virtual links
to virtual links
PSM
SDRAM
Plugin Subsystem
19
Gigabit Ethernet Line Card
GE
SUNI
GE
GE
SUNI
GE
SubstrateV2ProP100 (?)
4
GE
SUNI
GE
Power
GE
SUNI
Power
GE
20
techX Packet Processor Card
Power
TCAM
SDRAM
SDRAM
QDR
QDR 2Mx18b
QDR
QDR
Power
PP/HV2ProP100
40?625(160 pins)
512MB or 1GB
5
SDRAM
SubstrateV2ProP100
10
10?2.5 G
SDRAM
SDRAM
PP/HV2Pro P100
5
Power
40?625(160 pins)
TCAM
Power
QDR
QDR
QDR
QDR
21
Gigabit Ethernet Line Card
VNET Ethernet Frame
GE
SUNI
GE
GE
SUNI
GE
SubstrateV2ProP100 (?)
4
4
GE
SUNI
GE
Power
GE
SUNI
Power
GE
22
techX Packet Processor Card
23
IPv4 Virtual Packet Processor
SRAM
TCAM
SRAM
OUT
IN
CRL
QM
PSM
SDRAM
Plugin Subsystem
24
IPv4 Virtual Packet Processor
SRAM
TCAM
SRAM
OUT
IN
CRL
QM
PSM
SDRAM
Plugin Subsystem
25
IPv4 Virtual Packet Processor
SRAM
SRAM
OUT
IN
CRL
QM
PSM
SDRAM
26
IPv4 Virtual Packet Processor
27
IPv4 Virtual Packet Processor
SRAM
SRAM
TCAM
QM
RSQ
IN
CRL
OUT
PSM
SDRAM
Plugin Subsystem
28
IPv4 Virtual Packet Processor
SRAM
SRAM
QM
IN
CRL
OUT
PSM
SDRAM
29
IPv4 Virtual Packet Processor
SRAM
SRAM
IN
CRL
QM
OUT
PSM
SDRAM
30
IPv4 Virtual Packet Processor
SRAM
SRAM
IN
CRL
QM
OUT
PSM
SDRAM
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IN ? CRL

• ISAR ? CARL 4 words of 64 bits each
• Flags(16b)
• IVIN(5b)
• OVIN(5b)
• PPN(3b)
• QID(10b)
• PktPtr(20b)
• Saddr(32b)
• Daddr(32b)
• Sport(16b)
• Dport(16b)
• Protocol(8b)
• MTP(8b)
• TotalLength(11b)
• IpOptionsWord1(32b) (used for LFS)
• IpOptionsWord2(32b) (used for LFS)

IN
CRL
PSM
SDRAM
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IN ? CRL

• IN ? CRL
• Flags(16b)
• IVIN(5b) ? Input VI
• OVIN(5b)
• PPN(3b)
• QID(10b)
• PktPtr(20b)
• Saddr(32b)
• Daddr(32b)
• Sport(16b)
• Dport(16b)
• Protocol(8b)
• MTP(8b)
• TotalLength(11b)
• IpOptionsWord1(32b) (used for LFS)
• IpOptionsWord2(32b) (used for LFS)
• WHAT ELSE DO WE NEED for CRL?

33
CRL ? QM

• CARL ? QMGR 3 words of 32 bits each
• Flags(16b),
• Mb(1b)
• CopyCnt(2b)
• QID(10b)
• PPN(3b)
• Ovin(5b)
• PktPtr(20b)
• LFS Rate2(8b)
• LFS Rate1(8b)
• TotalLength(11b)

34
CRL ? QM

• CRL ? QM
• Plugin Bit
• Initial Copy bit
• Final Copy bit
• Drop bit
• CopyCnt(2b) for monitoring?
• Queue Set (Vitrual Interface) (3b)
• QID(10b) size?
• PktPtr(20b)
• TotalLength(11b)
• WHAT ELSE DO WE NEED for QM?

35
QM ? OUT

• QMGR ? OSAR 4 words of 32 bits each
• Flags(16b),
• LFS Rate2(8b)
• LFS Rate1(8b)
• QID(10b)
• Mb(1b)
• PktPtr(20b)
• QueueLength(24b)

SRAM
QM
OUT
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QM ? OUT

• QM ? OUT
• Plugin Bit
• Free Space Bit (i.e. free PSM memory)
• Single Chunk Bit
• PluginFlowIndex (QID) (10b)
• PktPtr(20b)
• Virtual Interface
• WHAT ELSE DO WE NEED for OUT?

SRAM
QM
OUT
37
Flags from NSP System

• Flags (8 bits)
• DP Drop Packet
• RC ReClassify packet
• CARL should do its thing (possibly again)
• NM No Match
• CARL found no match. Send packet somewhere for
  handling
• EX Exception packet
• Some kind of exception found, like IP options.
  Send packet somewhere for handling
• HO Header Only
• Special header only processing for SPC
• HR Header-only Return
• FM From LC/SW
• Directional bit for where packet came from Line
  Card or Switch
• TO To LC/SW
• Directional bit for where packet is going to
  Line Card or Switch
• Internal Flags (8 bits)
• DG Datagram packet
• Only CARL lookup result was route entry, put in
  datagram queue
• SB SPC bound packet

38
Flags for techX System

• Flags (8 bits)
• DP Drop Packet
• RC ReClassify packet
• NM No Match
• EX Exception packet
• How do we want to handle packets that need
  special processing or that dont match any route
  or filter?
• HO Header Only
• HR Header-only Return
• FM From LC/SW
• TO To LC/SW
• Internal Flags (8 bits)
• DG Datagram packet
• SB SPC bound packet
• SR SPC return packet
• IC Initial Copy do we need this?
• FC Final Copy
• Tells QM/OUT when packet payload can be released
  from PSM.
• LP LFS option present
• SC Single chunk packet (why was this needed?)

39
IN ? CRL

• IN ? CRL
• Flags(16b)
• Input VI
• PktPtr(20b)
• Saddr(32b)
• Daddr(32b)
• Sport(16b)
• Dport(16b)
• Protocol(8b)
• TotalLength(11b)

40
CRL ? QM

• CRL ? QM
• Flags(16b)
• CopyCnt(2b) for monitoring?
• QID(10b) size?
• Ovin(5b) ? VDST?
• PktPtr(20b)
• TotalLength(11b)

41
QM ? OUT

• QM ? OUT
• Flags(16b)
• OVIN (5b) ? VDST?
• PktPtr(20b)

SRAM
QM
OUT
42
Changes

• ISAR interface remove some header fields
• FIFOs change due to bram differences
• Virtex 4Kbits (up to 16 bits wide)
• V2Pro 16Kbits (up to 32 bits wide)
• Block rams for CARL fifos will need to be
  regenerated
• SRAM interface for CARL
• Asynchronous
• 125MHz internal rate
• 200 MHz DDR external rate
• May need to redo the clock latency for SRAM
  access
• Width issue
• New accesses are 72 bits wide
• Old access are 36 bits wide

43
Changes for QM

• SRAM interface
• Asynchronous
• 125MHz internal rate
• 200 MHz DDR external rate
• QDR vs. SDR
• May need to redo the clock latency for SRAM
  access
• Width issue
• New accesses are 72 bits wide
• Old access are 36 bits wide
• Support for multiple Virtual Links (max8)
• Each Virtual Link has
• A set of N queues (N256 or 512)
• 64 Datagram
• N-64 Reserved
• One set of Plugin Subsystem queues
• 256 or 512 queues.
• Clean up the intermix of SPC and LC queue handling