361 Computer Architecture Lecture 9: Designing Single Cycle Control

1
361Computer ArchitectureLecture 9 Designing
Single Cycle Control
2
Recap The MIPS Subset

• ADD and subtract
• add rd, rs, rt
• sub rd, rs, rt
• OR Imm
• ori rt, rs, imm16
• LOAD and STORE
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH
• beq rs, rt, imm16
• JUMP
• j target

3
Recap A Single Cycle Datapath

• We have everything except control signals
  (underline)
• Todays lecture will show you how to generate the
  control signals

Instructionlt310gt
Branch
Instruction Fetch Unit
Jump
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
4
The Big Picture Where are We Now?

• The Five Classic Components of a Computer
• Todays Topic Designing the Control for the
  Single Cycle Datapath

5
Outline of Todays Lecture

• Recap and Introduction
• Control for Register-Register Or Immediate
  instructions
• Control signals for Load, Store, Branch, Jump
• Building a local controller ALU Control
• The main controller
• Summary

6
RTL The ADD Instruction

• add rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt- Rrs Rrt The actual operation
• PC lt- PC 4 Calculate the next instructions
  address

7
Instruction Fetch Unit at the Beginning of Add /
Subtract

• Fetch the instruction from Instruction memory
  Instruction lt- memPC
• This is the same for all instructions

30
Addrlt312gt
30
PClt3128gt
Addrlt10gt
00
4
Target
Instruction Memory
30
Instructionlt250gt
26
30
32
30
1
Jump previous
Instructionlt310gt
30
SignExt
30
imm16
16
Instructionlt150gt
Branch previous
Zero previous
8
The Single Cycle Datapath during Add and Subtract

• Rrd lt- Rrs / - Rrt

Instructionlt310gt
Branch 0
Instruction Fetch Unit
Jump 0
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 1
0
1
Mux
ALUctr Add or Subtract
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
9
Instruction Fetch Unit at the End of Add and
Subtract

• PC lt- PC 4
• This is the same for all instructions except
  Branch and Jump

30
Addrlt312gt
30
PClt3128gt
Addrlt10gt
00
4
Target
Instruction Memory
30
Instructionlt250gt
26
30
32
30
1
Jump 0
Instructionlt310gt
30
SignExt
30
imm16
16
Instructionlt150gt
Branch 0
Zero x
10
The Single Cycle Datapath during Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
Branch 0
Instruction Fetch Unit
Jump 0
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Or
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 0
11
The Single Cycle Datapath during Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Or
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 0
12
The Single Cycle Datapath during Load

• Rrt lt- Data Memory Rrs SignExtimm16

Instructionlt310gt
Branch 0
Instruction Fetch Unit
Jump 0
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 1
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
13
The Single Cycle Datapath during Load

• Rrt lt- Data Memory Rrs SignExtimm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst 0
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 1
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
14
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
Branch 0
Instruction Fetch Unit
Jump 0
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 1
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
32
1
Data In
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
15
The Single Cycle Datapath during Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 1
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
32
Data In
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
16
The Single Cycle Datapath during Branch

• if (Rrs - Rrt 0) then Zero lt- 1
  else Zero lt- 0

Instructionlt310gt
Branch 1
Instruction Fetch Unit
Jump 0
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
ALUctr Subtract
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
17
Instruction Fetch Unit at the End of Branch

• if (Zero 1) then PC PC 4
  SignExtimm164 else PC PC 4

30
Addrlt312gt
30
PClt3128gt
Addrlt10gt
00
4
Target
Instruction Memory
30
Instructionlt250gt
26
30
32
30
1
Jump 0
Instructionlt310gt
30
SignExt
30
imm16
16
Assume Zero 1 to see the interesting case.
Instructionlt150gt
Branch 1
Zero 1
18
Instruction Fetch Unit at the End of Branch

• if (Zero 1) then PC PC 4
  SignExtimm164 else PC PC 4

Instructionlt310gt
nPC_sel
4
00
PC
Clk
imm16
19
The Single Cycle Datapath during Jump

• Nothing to do! Make sure control signals are set
  correctly!

Instructionlt310gt
Branch 0
Instruction Fetch Unit
Jump 1
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst x
0
1
Mux
Imm16
Rd
Rs
Rt
ALUctr x
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc x
ExtOp x
20
Instruction Fetch Unit at the End of Jump

• PC lt- PClt3129gt concat targetlt250gt concat
  00

30
Addrlt312gt
30
PClt3128gt
Addrlt10gt
00
4
Target
Instruction Memory
30
Instructionlt250gt
26
30
32
30
1
Jump 1
Instructionlt310gt
30
SignExt
30
imm16
16
Instructionlt150gt
Branch 0
Zero x
21
Step 4 Given Datapath RTL -gt Control
Instructionlt310gt
Inst Memory
lt2125gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
MemtoReg
MemWr
nPC_sel
ALUSrc
RegWr
RegDst
ExtOp
Equal
DATA PATH
22
A Summary of Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc RegB, ALUctr sub, RegDst rd,
RegWr, nPC_sel 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Z, ALUctr or, RegDst rt, RegWr,
nPC_sel 4 LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Sn, ALUctr add, MemtoReg,
RegDst rt, RegWr, nPC_sel 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrs PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add, MemWr,
nPC_sel 4 BEQ if ( Rrs Rrt ) then PC
lt PC sign_ext(Imm16) 00 else PC lt PC
4 nPC_sel Br, ALUctr sub
23
A Summary of the Control Signals
func
10 0000
See
10 0010
We Dont Care -)
Appendix A
op
00 0000
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
add, sub
I-type
ori, lw, sw, beq
J-type
jump
24
The Concept of Local Decoding
func
ALUctr
op
6
Main Control
3
ALUop
6
N
ALU
25
The Encoding of ALUop

• In this exercise, ALUop has to be 2 bits wide to
  represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, and (4) Subtract
• To implement the full MIPS ISA, ALUop hat to be 3
  bits to represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, (4) Subtract, and (5) And
  (Example andi)

R-type
ori
lw
sw
beq
jump
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUoplt20gt
1 00
0 10
0 00
0 00
xxx
0 01
26
The Decoding of the func Field
( P. 286 text)
27
The Truth Table for ALUctr
functlt30gt
Instruction Op.
0000
add
0010
subtract
0100
and
0101
or
1010
set-on-less-than
28
The Logic Equation for ALUctrlt2gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt2gt
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
X Y Z A
B C D
This makes funclt3gt a dont care

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt

!XY X!A!BC!D XA!BC!D
!XY X!BC!D
29
The Logic Equation for ALUctrlt1gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt1gt
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

• ALUctrlt1gt !ALUoplt2gt !ALUoplt0gt
• ALUoplt2gt !funclt2gt !funclt0gt

30
The Logic Equation for ALUctrlt0gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt0gt
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1

• ALUctrlt0gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

31
The ALU Control Block

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt
• ALUctrlt1gt !ALUoplt2gt !ALUoplt0gt
• ALUoplt2gt !funclt2gt !funclt0gt
• ALUctrlt0gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

32
Step 5 Logic for each control signal

• nPC_sel lt if (OP BEQ) then EQUAL else 0
• ALUsrc lt if (OP Rtype) then regB else
  immed
• ALUctr lt if (OP Rtype) then
  funct elseif (OP ORi) then OR elseif
  (OP BEQ) then sub else add
• ExtOp lt _____________
• MemWr lt _____________
• MemtoReg lt _____________
• RegWr lt_____________
• RegDst lt _____________

33
Step 5 Logic for each control signal

• nPC_sel lt if (OP BEQ) then EQUAL else 0
• ALUsrc lt if (OP Rtype) then regB else
  immed
• ALUctr lt if (OP Rtype) then
  funct elseif (OP ORi) then OR
  elseif (OP BEQ) then sub else
  add
• ExtOp lt if (OP ORi) then zero else sign
• MemWr lt (OP Store)
• MemtoReg lt (OP Load)
• RegWr lt if ((OP Store) (OP BEQ)) then
  0 else 1
• RegDst lt if ((OP Load) (OP ORi)) then
  0 else 1

34
The Truth Table for the Main Control
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegDst
1
0
0
x
x
x
ALUSrc
0
1
1
1
0
x
MemtoReg
0
0
1
x
x
x
RegWrite
1
1
1
0
0
0
MemWrite
0
0
0
1
0
0
Branch
0
0
0
0
1
0
Jump
0
0
0
0
0
1
ExtOp
x
0
1
1
x
x
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUop lt2gt
1
0
0
0
x
0
ALUop lt1gt
0
1
0
0
x
0
ALUop lt0gt
0
0
0
0
x
1
35
The Truth Table for RegWrite
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegWrite
1
1
1
x
x
x

• RegWrite R-type ori lw
• !oplt5gt !oplt4gt !oplt3gt !oplt2gt !oplt1gt
  !oplt0gt (R-type)
• !oplt5gt !oplt4gt oplt3gt oplt2gt !oplt1gt
  oplt0gt (ori)
• oplt5gt !oplt4gt !oplt3gt !oplt2gt oplt1gt
  oplt0gt (lw)

RegWrite
36
PLA Implementation of the Main Control
RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUoplt2gt
ALUoplt1gt
ALUoplt0gt
37
Putting it All Together A Single Cycle Processor
ALUop
ALU Control
ALUctr
3
func
RegDst
op
3
Main Control
6
Instrlt50gt
ALUSrc
6

Instrlt3126gt
Instructionlt310gt
Branch
Instruction Fetch Unit
Jump
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Instrlt150gt
Clk
ALUSrc
ExtOp
38
Clocking Methodology
Clk
Setup
Hold
Setup
Hold
Dont Care

• All storage elements are clocked by the same
  clock edge
• Cycle Time CLK-to-Q Longest Delay Path
  Setup Clock Skew
• (CLK-to-Q Shortest Delay Path - Clock Skew) gt
  Hold Time

39
Worst Case Timing (Load)
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memoey Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
ExtOp
Old Value
New Value
ALUSrc
Old Value
New Value
MemtoReg
Old Value
New Value
Register Write Occurs
RegWr
Old Value
New Value
Register File Access Time
busA
Old Value
New Value
Delay through Extender Mux
busB
Old Value
New Value
ALU Delay
Address
Old Value
New Value
Data Memory Access Time
busW
Old Value
New
40
Drawback of this Single Cycle Processor

• Long cycle time
• Cycle time must be long enough for the load
  instruction
• PCs Clock -to-Q
• Instruction Memory Access Time
• Register File Access Time
• ALU Delay (address calculation)
• Data Memory Access Time
• Register File Setup Time
• Clock Skew
• Cycle time is much longer than needed for all
  other instructions

41
Summary

• Single cycle datapath gt CPI1, CCT gt long
• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• Control is the hard part
• MIPS makes control easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates