Howd - Zur Hung

1
M2 Huffman Encoder Project
Howd - Zur Hung Eric Lai Wei Jie Lee Yu - Chiang
Lee Design Manager Jonathan P. Lee
Overall Project ObjectiveDesign a Low Power
Huffman Encoder
Presentation 9 April 4th, 2007
2
Huffman Encoder Project
Status
Design ProposalChip ArchitectureBehavioral
Verilog Implementation Size estimates/floorplannin
g Behavioral Verilog simulated Schematic Design
and SimulationComponent Layout Chip Layout
Simulation
3
Top Level Layout
4
Top Level Layout
Density 0.292
5
Schematic Simulation Results
SRAM Simulations with Sense Amp
6
Schematic Simulation Results
SRAM Problems

• Value does not fall to 0 but falls to 0.7V
  instead
• The bit and not_bit values are correct
• Fixes
• Tried to increase the nmos of the Sense Amp
  (didnt work)
• Increased strength of clk signal (didnt work)
• Use a latch?

7
SRAM with a latch Simulation
8
Schematic Simulation Results
SRAM Problems

• A minimal latch lets the value drop to around
  400mV (still investigating why)
• Larger size than our Sense Amp
• Fix our Sense Amp

9
Sense Amp versus Latch
10
Huffman Encoder Project
Problems

• Fix sense amp
• More buffering in layout
• Clean up some routing