SMP Implementing on Blackfin BF561

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SMP Implementingon BlackfinBF561
Graf Yang (???)Oct 18, 2008
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Agenda

• BF561 architecture
• Cache coherency solution
• Interrupt dispatch
• SMP status and applications
• SMP performance
• Limitations

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BF561 architecture
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BF561 architecture (cont.)?
Block diagram
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BF561 architecture (cont.)?

• Memory architecture
• L1 run at core speed
• L1 scratchpad sram 4K
• L1 instruction cache 16K
• L1 instruction sram 16K
• L1 data cache 32K
• L1 data sram 32K
• L2 run at 1/2 core speed
• Data or instruction sram 128K
• Shared by CoreA/B
• Cached (Disabled in SMP)?

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BF561 architecture (cont.)?
Compare to x86
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BF561 architecture (cont.)?
How to boot CoreB
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Cache coherency solution

• Why cache coherence
• Jiffies, Spin-lock, Semaphore, Mutex, ...

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Cache coherence solution (cont.)?

• Cache policy
• Main memory - Write Through
• Shared on chip SRAM (L2 SRAM) No cacheable
• Global Lock protect atomic data
• A special spin lock that stay in share on chip
  SRAM (L2 SRAM)?
• Operate functions _get_core_lock/_put_core_lock
• Parameter address of atomic data
• Spin lock based on global lock
• Invalidate all the data cache if the same lock
  has been got by another CPU
• Atomic ops based on global lock
• Protect the atomic operations
• Memory barrier
• Invalidate all the data cache

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Interrupt dispatch

• Peripheral interrupt trigger both cores
• Two kinds of irq handlers

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Interrupt dispatch (cont.)?

• Time monotonicity problem
• Using two Core timers causes not monotonic
• Using gptimer and 'handle_simple_irq' casues
  CoreB sticky
• Solution
• Use general purpose timer0 instead of Core
  timers
• Use handle_percpu_irq() instead of
  handle_simple_irq()?

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Interrupt dispatch (cont.)?

• Inter-processor interrupt SICB_SYSCR
• Write 1 to CA_supplement_int0 trigger an
  interrupt to CoreA
• Write 1 to CB_supplement_int0 trigger an
  interrupt to CoreB
• Interrupt handler write 1 to relevant bit to
  clear interrupt request
• Inter-processor interrupt implementing
• Per-cpu message queue
• Per-cpu spin lock
• Per-cpu interrupt

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SMP status and application (cont.)?

• SMP status
• 2008R1.5
• svn//sources.blackfin.uclinux.org/svn/uclinux-dis
  t/branches/2008R1/bfin_patch/smp_patch/
• Trunk
• svn//sources.blackfin.uclinux.org/svn/uclinux-dis
  t/trunk/bfin_patch/smp_patch/
• Application - Multi-task
• Video encoder/decoder - codec1 on CoreB, codec2
  on CoreA
• VoIP - codec on CoreB, network stack on CoreA

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SMP performance

• Whetstone test result
• Test software Whetstone
• Test Hardware BF561, Core Clock 600MHz, System
  Clock 100MHz
• Test Environment 1 UP
• Test Environment 2 SMP

• Performance analysis
• Invalidate entire data cache 79130 times in
  whetstone test

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Limitations

• Store routines to L1 I-SRAM
• Store shared data to L1 D-SRAM
• User multi-threads running on different Cores

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Questions?
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The End

• Thank you!